--- /dev/null
+
+ * [Apr/22/09]
+
+ Apply patches from folks at Ksplice.
+ Thank You Tim Abbott and Anders Kaseorg!
+
+ - Add prototypes for ud_set_user_opaque_data/ud_get_user_opaque_data.
+ - Remove autogenerated files from version control.
+ - autogen.sh wraps autoreconf.
+ - opgen.py takes path to optable.
+ - Use packing in instruction tables.
+ - Add support for setting the vendor to UD_VENDOR_ANY.
+ - Support for build as part of linux kernel.
+ - Support for 3 byte opcodes.
+ - Fix/Add instructions.
+
+ * [May/03/08] Fix: Makefile for HP-UX build.
+ Checked build on HP-UX, Solaris, FreeBSD, MacOS, Linux.
+ Potentially broken win32 build (need help.)
+ * [Apr/29/08] Fix: operand size cast for rcl, ror, etc. (Thanks to Hans)
+ Fix: support for implicit operands and segment
+ overrides (Thanks to Hans)
+ * [Mar/27/08] Add: new XML based optable generator.
+ Add: new build system based on libtool.
+ * [Dec/01/07] Fix: documentation buf: prefix fields
+ Fix: bufoverrun.c to include the right header.
+ * [Aug/05/07] Patch for DJGPP (Thanks to Robert Riebisch)
+ Removed "test" Target in tot Makefile (Thanks to Robert Riebisch)
+ New target:tests.
+ Misc. clean up top-of-tree Makefile.
+ Use config.h for package version
+ Review/cleanup FP Opcode map.
+ * [Dec/18/06] Fixed: Printf warnings.
+ Fixed: set_input_buffered to set_input_buffer in documentation.
+ Added support for INTEL VMX instructions.
+ API addition: ud_set_vendor(): UD_VENDOR_{INTEL, AMD}.
+ Fixed: Handling of invalid combination of bytes. No more
+ input re-syncing.
+ Added Makefiles for win32 build. (Thanks to Xi Hang).
+ Added Makefile.standalone for "Standalone Udis86".
+ Fixed: u->inp_end initialization bug.
+ Fixed: swapgs only in 64bit mode.
+ * [Oct/27/06] 0xF1 is now int1.
+ Fixed: cast prefix for Group1_op80/82/C0/D0 instructions.
+ Fixed: lmsw
+ Added support for Udis86 Standalone.
+ * [Sep/18/06] Fixed: Missing support for o32 for in/out instructions.
+ * [Jul/26/06] Fixed: Missing REX.W in Group1_op83 instructions.
+ * [Jul/16/06] Fixed: rex.b on [rip+disp]
+ * [Jul/15/06] Fixed: Wrongly printing "loopnz" as "loopn" (Thanks to Sanjay Patel)
+ Fixed: Wrongly decoding "out Ib, AL" (Thanks to Sanjay Patel)
+ * [Jun/8/06] Missing instructions added. (As per AMD64 Manual Vol3 Rev 3.11
+ Dec 2005)
+ Fixed minor decoder issues. (Thanks to Sanjay Patel)
+ Fixed issues with input stream buffer. (Thanks to Sanjay Patel)
+ * [May/18/06] Fixed issues with handling of 64-bit values.
+ Fixed bug in syntax generation for immediate operands in branch
+ instructions.
+ Fixed decoding of (G, W) operands.
+ * [May/12/06] Added support for data types in MS VC++.
+ * [May/11/06] Fixed portability issues concerning inp_uintXX functions in
+ input.c and 64-bit casting in syn-intel/syn-att.c (Thanks to
+ Sanjay Patel)
--- /dev/null
+Installation Instructions
+*************************
+
+Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005,
+2006 Free Software Foundation, Inc.
+
+This file is free documentation; the Free Software Foundation gives
+unlimited permission to copy, distribute and modify it.
+
+Basic Installation
+==================
+
+Briefly, the shell commands `./configure; make; make install' should
+configure, build, and install this package. The following
+more-detailed instructions are generic; see the `README' file for
+instructions specific to this package.
+
+ The `configure' shell script attempts to guess correct values for
+various system-dependent variables used during compilation. It uses
+those values to create a `Makefile' in each directory of the package.
+It may also create one or more `.h' files containing system-dependent
+definitions. Finally, it creates a shell script `config.status' that
+you can run in the future to recreate the current configuration, and a
+file `config.log' containing compiler output (useful mainly for
+debugging `configure').
+
+ It can also use an optional file (typically called `config.cache'
+and enabled with `--cache-file=config.cache' or simply `-C') that saves
+the results of its tests to speed up reconfiguring. Caching is
+disabled by default to prevent problems with accidental use of stale
+cache files.
+
+ If you need to do unusual things to compile the package, please try
+to figure out how `configure' could check whether to do them, and mail
+diffs or instructions to the address given in the `README' so they can
+be considered for the next release. If you are using the cache, and at
+some point `config.cache' contains results you don't want to keep, you
+may remove or edit it.
+
+ The file `configure.ac' (or `configure.in') is used to create
+`configure' by a program called `autoconf'. You need `configure.ac' if
+you want to change it or regenerate `configure' using a newer version
+of `autoconf'.
+
+The simplest way to compile this package is:
+
+ 1. `cd' to the directory containing the package's source code and type
+ `./configure' to configure the package for your system.
+
+ Running `configure' might take a while. While running, it prints
+ some messages telling which features it is checking for.
+
+ 2. Type `make' to compile the package.
+
+ 3. Optionally, type `make check' to run any self-tests that come with
+ the package.
+
+ 4. Type `make install' to install the programs and any data files and
+ documentation.
+
+ 5. You can remove the program binaries and object files from the
+ source code directory by typing `make clean'. To also remove the
+ files that `configure' created (so you can compile the package for
+ a different kind of computer), type `make distclean'. There is
+ also a `make maintainer-clean' target, but that is intended mainly
+ for the package's developers. If you use it, you may have to get
+ all sorts of other programs in order to regenerate files that came
+ with the distribution.
+
+Compilers and Options
+=====================
+
+Some systems require unusual options for compilation or linking that the
+`configure' script does not know about. Run `./configure --help' for
+details on some of the pertinent environment variables.
+
+ You can give `configure' initial values for configuration parameters
+by setting variables in the command line or in the environment. Here
+is an example:
+
+ ./configure CC=c99 CFLAGS=-g LIBS=-lposix
+
+ *Note Defining Variables::, for more details.
+
+Compiling For Multiple Architectures
+====================================
+
+You can compile the package for more than one kind of computer at the
+same time, by placing the object files for each architecture in their
+own directory. To do this, you can use GNU `make'. `cd' to the
+directory where you want the object files and executables to go and run
+the `configure' script. `configure' automatically checks for the
+source code in the directory that `configure' is in and in `..'.
+
+ With a non-GNU `make', it is safer to compile the package for one
+architecture at a time in the source code directory. After you have
+installed the package for one architecture, use `make distclean' before
+reconfiguring for another architecture.
+
+Installation Names
+==================
+
+By default, `make install' installs the package's commands under
+`/usr/local/bin', include files under `/usr/local/include', etc. You
+can specify an installation prefix other than `/usr/local' by giving
+`configure' the option `--prefix=PREFIX'.
+
+ You can specify separate installation prefixes for
+architecture-specific files and architecture-independent files. If you
+pass the option `--exec-prefix=PREFIX' to `configure', the package uses
+PREFIX as the prefix for installing programs and libraries.
+Documentation and other data files still use the regular prefix.
+
+ In addition, if you use an unusual directory layout you can give
+options like `--bindir=DIR' to specify different values for particular
+kinds of files. Run `configure --help' for a list of the directories
+you can set and what kinds of files go in them.
+
+ If the package supports it, you can cause programs to be installed
+with an extra prefix or suffix on their names by giving `configure' the
+option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'.
+
+Optional Features
+=================
+
+Some packages pay attention to `--enable-FEATURE' options to
+`configure', where FEATURE indicates an optional part of the package.
+They may also pay attention to `--with-PACKAGE' options, where PACKAGE
+is something like `gnu-as' or `x' (for the X Window System). The
+`README' should mention any `--enable-' and `--with-' options that the
+package recognizes.
+
+ For packages that use the X Window System, `configure' can usually
+find the X include and library files automatically, but if it doesn't,
+you can use the `configure' options `--x-includes=DIR' and
+`--x-libraries=DIR' to specify their locations.
+
+Specifying the System Type
+==========================
+
+There may be some features `configure' cannot figure out automatically,
+but needs to determine by the type of machine the package will run on.
+Usually, assuming the package is built to be run on the _same_
+architectures, `configure' can figure that out, but if it prints a
+message saying it cannot guess the machine type, give it the
+`--build=TYPE' option. TYPE can either be a short name for the system
+type, such as `sun4', or a canonical name which has the form:
+
+ CPU-COMPANY-SYSTEM
+
+where SYSTEM can have one of these forms:
+
+ OS KERNEL-OS
+
+ See the file `config.sub' for the possible values of each field. If
+`config.sub' isn't included in this package, then this package doesn't
+need to know the machine type.
+
+ If you are _building_ compiler tools for cross-compiling, you should
+use the option `--target=TYPE' to select the type of system they will
+produce code for.
+
+ If you want to _use_ a cross compiler, that generates code for a
+platform different from the build platform, you should specify the
+"host" platform (i.e., that on which the generated programs will
+eventually be run) with `--host=TYPE'.
+
+Sharing Defaults
+================
+
+If you want to set default values for `configure' scripts to share, you
+can create a site shell script called `config.site' that gives default
+values for variables like `CC', `cache_file', and `prefix'.
+`configure' looks for `PREFIX/share/config.site' if it exists, then
+`PREFIX/etc/config.site' if it exists. Or, you can set the
+`CONFIG_SITE' environment variable to the location of the site script.
+A warning: not all `configure' scripts look for a site script.
+
+Defining Variables
+==================
+
+Variables not defined in a site shell script can be set in the
+environment passed to `configure'. However, some packages may run
+configure again during the build, and the customized values of these
+variables may be lost. In order to avoid this problem, you should set
+them in the `configure' command line, using `VAR=value'. For example:
+
+ ./configure CC=/usr/local2/bin/gcc
+
+causes the specified `gcc' to be used as the C compiler (unless it is
+overridden in the site shell script).
+
+Unfortunately, this technique does not work for `CONFIG_SHELL' due to
+an Autoconf bug. Until the bug is fixed you can use this workaround:
+
+ CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash
+
+`configure' Invocation
+======================
+
+`configure' recognizes the following options to control how it operates.
+
+`--help'
+`-h'
+ Print a summary of the options to `configure', and exit.
+
+`--version'
+`-V'
+ Print the version of Autoconf used to generate the `configure'
+ script, and exit.
+
+`--cache-file=FILE'
+ Enable the cache: use and save the results of the tests in FILE,
+ traditionally `config.cache'. FILE defaults to `/dev/null' to
+ disable caching.
+
+`--config-cache'
+`-C'
+ Alias for `--cache-file=config.cache'.
+
+`--quiet'
+`--silent'
+`-q'
+ Do not print messages saying which checks are being made. To
+ suppress all normal output, redirect it to `/dev/null' (any error
+ messages will still be shown).
+
+`--srcdir=DIR'
+ Look for the package's source code in directory DIR. Usually
+ `configure' can determine that directory automatically.
+
+`configure' also accepts some other, not widely useful, options. Run
+`configure --help' for more details.
+
--- /dev/null
+Copyright (c) 2002, 2003, 2004, 2005, 2006, 2007, 2008 <vivek@sig9.com>
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--- /dev/null
+ACLOCAL_AMFLAGS = -I build/m4
+
+SUBDIRS = libudis86 . udcli . tests . docs
+
+GENERATED = autom4te.cache \
+ aclocal.m4 \
+ configure \
+ build \
+ *.in \
+ libudis86/*.in \
+ udcli/*.in \
+ tests/*.in \
+ docs/*.in
+
+include_ladir = ${includedir}
+include_la_HEADERS = udis86.h
+
+.PHONY: libudis86 udcli tests
+
+libudis86:
+ $(MAKE) -C $@
+
+udcli: libudis86
+ $(MAKE) -C $@
+
+tests: check
+
+maintainer-clean-local:
+ rm -rf $(GENERATED)
--- /dev/null
+# Makefile
+# udis86 - udis86 disassembler for x86(x86-64)
+#
+
+all:
+ cd libudis86 && $(MAKE) -f Makefile.win32
+ cd udcli && $(MAKE) -f Makefile.win32
+clean:
+ cd libudis86 && $(MAKE) clean -f Makefile.win32
+ cd udcli && $(MAKE) clean -f Makefile.win32
+
--- /dev/null
+See docs/udis86.pdf
--- /dev/null
+#!/bin/bash
+#
+if [ ! -e build/m4 ]; then mkdir -p build/m4; fi
+autoreconf --force -v --install || ( echo "autogen: autoreconf -i failed." && false )
--- /dev/null
+#
+#
+AC_PREREQ(2.59)
+AC_INIT([udis86], [1.7], [vivek@sig9.com])
+AC_CONFIG_AUX_DIR(build)
+AC_CONFIG_MACRO_DIR([build/m4])
+AM_MAINTAINER_MODE
+
+# Determine the build host; we notify automake of Windows builds, so it can
+# pass proper parameters for building DLLs to the linker.
+AC_CANONICAL_HOST
+case "$host_os" in
+ mingw32*)
+ TARGET_OS=windows
+ AC_LIBTOOL_WIN32_DLL
+ ;;
+esac
+
+# Initialize the automake subsystem.
+# In case we have a Windows build, we pass a TARGET_WINDOWS conditional to
+# automake.
+AM_INIT_AUTOMAKE([-Wall -Werror foreign])
+AM_CONDITIONAL(TARGET_WINDOWS, test "$TARGET_OS" = windows)
+
+AC_PROG_CC
+AC_DISABLE_SHARED
+AC_PROG_LIBTOOL
+AM_PROG_CC_C_O
+
+# If this is a gnu compiler, pass -Wall
+if test "$ac_cv_c_compiler_gnu" = "yes"; then
+ CFLAGS="$CFLAGS -Wall"
+fi
+
+AC_CONFIG_HEADERS(config.h)
+AC_CONFIG_FILES([
+ Makefile
+ libudis86/Makefile
+ udcli/Makefile
+ tests/Makefile
+ docs/Makefile
+])
+
+AC_OUTPUT
--- /dev/null
+docdir = ${datadir}/docs
+dist_doc_DATA = udis86.odt udis86.pdf index.html style.css ss.jpg x86optable.xml x86optable.xsl
--- /dev/null
+<html>
+<head>
+<title>Udis86 - Disassembler Library for x86 and AMD64 (x86-64)</title>
+<style type="text/css">@import 'style.css';</style>
+</head>
+<body>
+<div id="topbar"><h1>Udis86 - Disassembler Library for x86 and AMD64</h1></div>
+
+<div id="wrapper">
+
+<div id="content">
+
+<div>
+ <big>
+ <a href="udis86.pdf">Documentation</a> ·
+ <a href="x86optable.xml">XML Optable</a> ·
+ <a href="#help">Help!</a> ·
+ <a href="#author">Author</a> ·
+ <a href="http://udis86.cvs.sourceforge.net/udis86/ud/CHANGES?view=markup&pathrev=HEAD">Changes</a> ·
+ <a href="http://sourceforge.net/projects/udis86">SF Project Page</a>
+ </big>
+</div>
+
+
+<p>Udis86 is an easy-to-use minimalistic disassembler library (<i>libudis86</i>)
+for the x86 and AMD64 (x86-64) range of instruction set architectures. The primary
+intent of the design and development of udis86 is to aid software development
+projects that entail binary code analysis.</p>
+
+<div class="box">
+ <big>Latest Release: <a href="http://prdownloads.sourceforge.net/udis86/udis86-1.7.tar.gz?download">udis86-1.7.tar.gz</a></big>
+</div>
+
+<h2>libudis86</h2>
+ <ol>
+ <li>Full support for the <i>x86 and x86-64 (AMD64)</i> range of instruction set
+ architectures.</li>
+ <li>Full support for all <i> AMD-V, INTEL-VMX, MMX, SSE, SSE2, SSE3, FPU(x87), and
+ AMD 3Dnow! </i> instructions.</li>
+ <li>Supports 16bit, 32bit, and 64bit disassembly modes.</li>
+ <li>Supports instruction meta-data using XML based decode tables.</li>
+ <li>Generates output in <i>AT&T</i> or <i>INTEL</i> assembler language syntaxes.</li>
+ <li>Supports flexbile input methods: File, Buffer, and Hooks.</li>
+ <li>Thread-safe and Reentrant.</li>
+ <li>Clean and very easy-to-use API.</li>
+ </ol>
+
+<h2>udcli</h2>
+
+ A front-end incarnation of this library, udcli is a small command-line tool
+ for your quick disassembly needs.
+ <br/>
+ <div style="text-align:center; padding: 1em;">
+ <img src="ss.jpg" style="border: 1px double; padding: 2px;"/>
+ </div>
+
+<a name="help"></a>
+<h2>Help Needed</h2>
+
+ I am looking for developers who can help me with udis86 in the following
+ areas,
+
+ <ul>
+ <li>Maintenance of the build system (especially for Windows)</li>
+ <li>Maintenance of the x86optable (adding new instructions, meta-data, etc.)</li>
+ <li>Testing udis86</li>
+ <li>Writing extensions for dynamic languages.</li>
+ </ul>
+
+ If you are interested, let me know at vivekATsig9DOTcom.
+
+<a name="author"></a>
+<h2>Author</h2>
+
+<p>Udis86 is a creation of <a href="http://sig9.com/vivek/">Vivek Mohan</a>.
+You can reach me at <i>vivek[at]sig9[dot]com</i>. Please let me know if you are
+using udis86, have ideas for it, or would like to comment on it.</p>
+
+
+<div style="text-align:center"><small>© 2006, 2007, 2008 Vivek Mohan</small></div>
+</div>
+</div>
+</body>
+</html>
--- /dev/null
+body {
+ font: 76%, sans-serif;
+ background-color: #fff;
+ margin: 0;
+ padding: 0;
+}
+
+#topbar {
+ margin-top: 0px;
+ padding: 1em;
+ background-color: skyblue;
+ color: navy;
+}
+
+#topbar h1 {
+ padding: 0;
+ margin: 0;
+ font: 2em, sans-serif;
+ font-weight: bold;
+}
+
+#wrapper {
+ width: 750px;
+}
+
+#menu {
+}
+#content a {
+ text-decoration: none;
+ color: navy;
+// border-bottom: 1px solid;
+}
+
+#content {
+ margin-left: 40px;
+ font-size: 1.1em;
+ line-height: 1.4em;
+ padding: 1em;
+ vertical-align: top;
+ border-left: 1px solid skyblue;
+ border-right: 1px solid skyblue;
+}
+
+.box {
+ background-color: #efefef;
+ border: 1px dotted #aaa;
+ padding: .5em;
+}
+
+li {
+ margin-bottom: .5em;
+}
+
+pre {
+ padding: .5em;
+ background-color: #f5f5f5;
+ font-size: 1.1em;
+ border: 1px solid #999;
+}
+
+code {
+ font-size: 1.2em;
+}
+
+ul {
+ margin: 1em;
+}
--- /dev/null
+<?xml version="1.0"?>
+<?xml-stylesheet href="x86optable.xsl" type="text/xsl"?>
+<x86optable>
+
+ <!--
+ udis86 - docs/x86optable.xml
+
+ UDIS86 X86/AMD64/IA32/IA32e OPCODE TABLE
+
+ Copyright (c) 2008, 2009 Vivek Thampi
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+ -->
+
+ <instruction mnemonic="3dnow">
+ <opcode> ; 0f 0f ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="aaa">
+ <opcode mode="inv64"> ; 37 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="aad">
+ <opcode mode="inv64"> ; d5 ; Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="aam">
+ <opcode mode="inv64"> ; d4 ; Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="aas">
+ <opcode mode="inv64"> ; 3f ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="adc">
+ <opcode> aso rexr rexx rexb ; 10 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 11 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 12 ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 13 ; Gv Ev </opcode>
+ <opcode> ; 14 ; AL Ib </opcode>
+ <opcode> oso rexw ; 15 ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; 80 /2 ; Eb Ib </opcode>
+ <opcode cast="1" mode="inv64"> aso rexr rexx rexb ; 82 /2 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 81 /2 ; Ev Iz </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 83 /2 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="add">
+ <opcode> aso rexr rexx rexb ; 00 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 01 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 02 ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 03 ; Gv Ev </opcode>
+ <opcode> ; 04 ; AL Ib </opcode>
+ <opcode> oso rexw ; 05 ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; 80 /0 ; Eb Ib </opcode>
+ <opcode cast="1" mode="inv64"> aso rexr rexx rexb ; 82 /0 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 81 /0 ; Ev Iz </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 83 /0 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="addpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 58 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="addps">
+ <opcode> aso rexr rexx rexb ; 0f 58 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="addsd">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 58 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="addss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 58 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="addsubpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f d0 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="addsubps">
+ <opcode> aso rexr rexx rexb ; ssef2 0f d0 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="and">
+ <opcode> aso rexr rexx rexb ; 20 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 21 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 22 ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 23 ; Gv Ev </opcode>
+ <opcode> ; 24 ; AL Ib </opcode>
+ <opcode> oso rexw ; 25 ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; 80 /4 ; Eb Ib </opcode>
+ <opcode cast="1" mode="inv64"> aso rexr rexx rexb ; 82 /4 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 81 /4 ; Ev Iz </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 83 /4 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="andpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 54 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="andps">
+ <opcode> aso rexr rexx rexb ; 0f 54 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="andnpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 55 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="andnps">
+ <opcode> aso rexr rexx rexb ; 0f 55 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="arpl">
+ <opcode mode="inv64"> aso ; 63 /M16 ; Ew Gw </opcode>
+ <opcode mode="inv64"> aso ; 63 /M32 ; Ew Gw </opcode>
+ </instruction>
+
+ <instruction mnemonic="movsxd">
+ <opcode cast="2"> aso oso rexw rexx rexr rexb ; 63 /M64 ; Gv Ed </opcode>
+ </instruction>
+
+ <instruction mnemonic="bound">
+ <opcode mode="inv64"> aso oso ; 62 ; Gv M </opcode>
+ </instruction>
+
+ <instruction mnemonic="bsf">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f bc ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="bsr">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f bd ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="bswap">
+ <opcode> oso rexw rexb ; 0f c8 ; rAXr8 </opcode>
+ <opcode> oso rexw rexb ; 0f c9 ; rCXr9 </opcode>
+ <opcode> oso rexw rexb ; 0f ca ; rDXr10 </opcode>
+ <opcode> oso rexw rexb ; 0f cb ; rBXr11 </opcode>
+ <opcode> oso rexw rexb ; 0f cc ; rSPr12 </opcode>
+ <opcode> oso rexw rexb ; 0f cd ; rBPr13 </opcode>
+ <opcode> oso rexw rexb ; 0f ce ; rSIr14 </opcode>
+ <opcode> oso rexw rexb ; 0f cf ; rDIr15 </opcode>
+ </instruction>
+
+ <instruction mnemonic="bt">
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 0F BA /4 ; Ev Ib </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 0f a3 ; Ev Gv </opcode>
+ </instruction>
+
+ <instruction mnemonic="btc">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f bb ; Ev Gv </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 0F BA /7 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="btr">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f b3 ; Ev Gv </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 0F BA /6 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="bts">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f ab ; Ev Gv </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 0F BA /5 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="call">
+ <opcode mode="def64" cast="1"> aso oso rexw rexr rexx rexb ; FF /2 ; Ev </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; FF /3 ; Ep </opcode>
+ <opcode mode="def64"> oso ; e8 ; Jz </opcode>
+ <opcode mode="inv64"> oso ; 9a ; Ap </opcode>
+ </instruction>
+
+ <instruction mnemonic="cbw">
+ <opcode> oso rexw ; 98 /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cwde">
+ <opcode> oso rexw ; 98 /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cdqe">
+ <opcode> oso rexw ; 98 /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="clc">
+ <opcode> f8 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cld">
+ <opcode> fc ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="clflush">
+ <opcode> aso rexw rexr rexx rexb ; 0F AE /7 /mod=!11 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="clgi">
+ <opcode> 0F 01 /3 /mod=11 /rm=5 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="cli">
+ <opcode> fa ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="clts">
+ <opcode> 0f 06 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmc">
+ <opcode> f5 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovo">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 40 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovno">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 41 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovb">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 42 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovae">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 43 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovz">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 44 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovnz">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 45 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovbe">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 46 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmova">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 47 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovs">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 48 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovns">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 49 ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovp">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 4a ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovnp">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 4b ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovl">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 4c ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovge">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 4d ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovle">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 4e ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmovg">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 4f ; Gv Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmp">
+ <opcode> aso rexr rexx rexb ; 38 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 39 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 3a ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 3b ; Gv Ev </opcode>
+ <opcode> ; 3c ; AL Ib </opcode>
+ <opcode> oso rexw ; 3d ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; 80 /7 ; Eb Ib </opcode>
+ <opcode cast="1" mode="inv64"> aso rexr rexx rexb ; 82 /7 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 81 /7 ; Ev Iz </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 83 /7 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmppd">
+ <opcode> aso rexr rexx rexb ; sse66 0f c2 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmpps">
+ <opcode> aso rexr rexx rexb ; 0f c2 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmpsb">
+ <opcode> a6 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmpsw">
+ <opcode> oso rexw ; a7 /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmpsd">
+ <opcode> oso rexw ; a7 /O32 ; </opcode>
+ <opcode> aso rexr rexx rexb ; ssef2 0f c2 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmpsq">
+ <opcode> oso rexw ; a7 /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmpss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f c2 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmpxchg">
+ <opcode> aso rexr rexx rexb ; 0f b0 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 0f b1 ; Ev Gv </opcode>
+ </instruction>
+
+ <instruction mnemonic="cmpxchg8b">
+ <opcode> aso rexr rexx rexb ; 0F C7 /1 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="comisd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 2f ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="comiss">
+ <opcode> aso rexr rexx rexb ; 0f 2f ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cpuid">
+ <opcode> 0f a2 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtdq2pd">
+ <opcode> aso rexr rexx rexb ; ssef3 0f e6 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtdq2ps">
+ <opcode> aso rexr rexx rexb ; 0f 5b ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtpd2dq">
+ <opcode> aso rexr rexx rexb ; ssef2 0f e6 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtpd2pi">
+ <opcode> aso rexr rexx rexb ; sse66 0f 2d ; P W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtpd2ps">
+ <opcode> aso rexr rexx rexb ; sse66 0f 5a ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtpi2ps">
+ <opcode> aso rexr rexx rexb ; 0f 2a ; V Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtpi2pd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 2a ; V Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtps2dq">
+ <opcode> aso rexr rexx rexb ; sse66 0f 5b ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtps2pi">
+ <opcode> aso rexr rexx rexb ; 0f 2d ; P W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtps2pd">
+ <opcode> aso rexr rexx rexb ; 0f 5a ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtsd2si">
+ <opcode cast="1"> aso rexr rexx rexb ; ssef2 0f 2d ; Gvw W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtsd2ss">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 5a ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtsi2ss">
+ <opcode cast="2"> aso rexr rexx rexb ; ssef3 0f 2a ; V Ex </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtss2si">
+ <opcode cast="1"> aso rexr rexx rexb ; ssef3 0f 2d ; Gvw W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtss2sd">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 5a ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvttpd2pi">
+ <opcode> aso rexr rexx rexb ; sse66 0f 2c ; P W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvttpd2dq">
+ <opcode> ; sse66 0f e6 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvttps2dq">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 5b ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvttps2pi">
+ <opcode> aso rexr rexx rexb ; 0f 2c ; P W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvttsd2si">
+ <opcode cast="1"> aso rexr rexx rexb ; ssef2 0f 2c ; Gvw W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvtsi2sd">
+ <opcode cast="2"> aso rexw rexr rexx rexb ; ssef2 0f 2a ; V Ex </opcode>
+ </instruction>
+
+ <instruction mnemonic="cvttss2si">
+ <opcode cast="1"> aso rexr rexx rexb ; ssef3 0f 2c ; Gvw W </opcode>
+ </instruction>
+
+ <instruction mnemonic="cwd">
+ <opcode> oso rexw ; 99 /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cdq">
+ <opcode> oso rexw ; 99 /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="cqo">
+ <opcode> oso rexw ; 99 /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="daa">
+ <opcode mode="inv64"> ; 27 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="das">
+ <opcode mode="inv64"> ; 2f ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="dec">
+ <opcode> oso ; 48 ; eAX </opcode>
+ <opcode> oso ; 49 ; eCX </opcode>
+ <opcode> oso ; 4a ; eDX </opcode>
+ <opcode> oso ; 4b ; eBX </opcode>
+ <opcode> oso ; 4c ; eSP </opcode>
+ <opcode> oso ; 4d ; eBP </opcode>
+ <opcode> oso ; 4e ; eSI </opcode>
+ <opcode> oso ; 4f ; eDI </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; FE /1 ; Eb </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; FF /1 ; Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="div">
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; F7 /6 ; Ev </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; F6 /6 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="divpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 5e ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="divps">
+ <opcode> aso rexr rexx rexb ; 0f 5e ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="divsd">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 5e ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="divss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 5e ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="emms">
+ <opcode> 0f 77 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="enter">
+ <opcode mode="def64 depM"> ; c8 ; Iw Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="f2xm1">
+ <opcode> 0F D9 /mod=11 /x87=30 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fabs">
+ <opcode> 0F D9 /mod=11 /x87=21 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fadd">
+ <class> X87 </class>
+ <opcode cast="1"> aso rexr rexx rexb ; DC /mod=!11 /0 ; Mq </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; D8 /mod=!11 /0 ; Md </opcode>
+ <opcode> DC /mod=11 /x87=00 ; ST0 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=01 ; ST1 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=02 ; ST2 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=03 ; ST3 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=04 ; ST4 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=05 ; ST5 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=06 ; ST6 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=07 ; ST7 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=00 ; ST0 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=01 ; ST0 ST1 </opcode>
+ <opcode> D8 /mod=11 /x87=02 ; ST0 ST2 </opcode>
+ <opcode> D8 /mod=11 /x87=03 ; ST0 ST3 </opcode>
+ <opcode> D8 /mod=11 /x87=04 ; ST0 ST4 </opcode>
+ <opcode> D8 /mod=11 /x87=05 ; ST0 ST5 </opcode>
+ <opcode> D8 /mod=11 /x87=06 ; ST0 ST6 </opcode>
+ <opcode> D8 /mod=11 /x87=07 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="faddp">
+ <opcode> DE /mod=11 /x87=00 ; ST0 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=01 ; ST1 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=02 ; ST2 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=03 ; ST3 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=04 ; ST4 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=05 ; ST5 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=06 ; ST6 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=07 ; ST7 ST0 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fbld">
+ <class> X87 </class>
+ <opcode> aso rexr rexx rexb ; DF /mod=!11 /4 ; Mt </opcode>
+ </instruction>
+
+ <instruction mnemonic="fbstp">
+ <class> X87 </class>
+ <opcode> aso rexr rexx rexb ; DF /mod=!11 /6 ; Mt </opcode>
+ </instruction>
+
+ <instruction mnemonic="fchs">
+ <class> X87 </class>
+ <opcode> D9 /mod=11 /x87=20 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="fclex">
+ <opcode> DB /mod=11 /x87=22 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcmovb">
+ <opcode> DA /mod=11 /x87=00 ; ST0 ST0 </opcode>
+ <opcode> DA /mod=11 /x87=01 ; ST0 ST1 </opcode>
+ <opcode> DA /mod=11 /x87=02 ; ST0 ST2 </opcode>
+ <opcode> DA /mod=11 /x87=03 ; ST0 ST3 </opcode>
+ <opcode> DA /mod=11 /x87=04 ; ST0 ST4 </opcode>
+ <opcode> DA /mod=11 /x87=05 ; ST0 ST5 </opcode>
+ <opcode> DA /mod=11 /x87=06 ; ST0 ST6 </opcode>
+ <opcode> DA /mod=11 /x87=07 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcmove">
+ <opcode> DA /mod=11 /x87=08 ; ST0 ST0 </opcode>
+ <opcode> DA /mod=11 /x87=09 ; ST0 ST1 </opcode>
+ <opcode> DA /mod=11 /x87=0A ; ST0 ST2 </opcode>
+ <opcode> DA /mod=11 /x87=0B ; ST0 ST3 </opcode>
+ <opcode> DA /mod=11 /x87=0C ; ST0 ST4 </opcode>
+ <opcode> DA /mod=11 /x87=0D ; ST0 ST5 </opcode>
+ <opcode> DA /mod=11 /x87=0E ; ST0 ST6 </opcode>
+ <opcode> DA /mod=11 /x87=0F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcmovbe">
+ <opcode> DA /mod=11 /x87=10 ; ST0 ST0 </opcode>
+ <opcode> DA /mod=11 /x87=11 ; ST0 ST1 </opcode>
+ <opcode> DA /mod=11 /x87=12 ; ST0 ST2 </opcode>
+ <opcode> DA /mod=11 /x87=13 ; ST0 ST3 </opcode>
+ <opcode> DA /mod=11 /x87=14 ; ST0 ST4 </opcode>
+ <opcode> DA /mod=11 /x87=15 ; ST0 ST5 </opcode>
+ <opcode> DA /mod=11 /x87=16 ; ST0 ST6 </opcode>
+ <opcode> DA /mod=11 /x87=17 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcmovu">
+ <opcode> DA /mod=11 /x87=18 ; ST0 ST0 </opcode>
+ <opcode> DA /mod=11 /x87=19 ; ST0 ST1 </opcode>
+ <opcode> DA /mod=11 /x87=1A ; ST0 ST2 </opcode>
+ <opcode> DA /mod=11 /x87=1B ; ST0 ST3 </opcode>
+ <opcode> DA /mod=11 /x87=1C ; ST0 ST4 </opcode>
+ <opcode> DA /mod=11 /x87=1D ; ST0 ST5 </opcode>
+ <opcode> DA /mod=11 /x87=1E ; ST0 ST6 </opcode>
+ <opcode> DA /mod=11 /x87=1F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcmovnb">
+ <opcode> DB /mod=11 /x87=00 ; ST0 ST0 </opcode>
+ <opcode> DB /mod=11 /x87=01 ; ST0 ST1 </opcode>
+ <opcode> DB /mod=11 /x87=02 ; ST0 ST2 </opcode>
+ <opcode> DB /mod=11 /x87=03 ; ST0 ST3 </opcode>
+ <opcode> DB /mod=11 /x87=04 ; ST0 ST4 </opcode>
+ <opcode> DB /mod=11 /x87=05 ; ST0 ST5 </opcode>
+ <opcode> DB /mod=11 /x87=06 ; ST0 ST6 </opcode>
+ <opcode> DB /mod=11 /x87=07 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcmovne">
+ <opcode> DB /mod=11 /x87=08 ; ST0 ST0 </opcode>
+ <opcode> DB /mod=11 /x87=09 ; ST0 ST1 </opcode>
+ <opcode> DB /mod=11 /x87=0A ; ST0 ST2 </opcode>
+ <opcode> DB /mod=11 /x87=0B ; ST0 ST3 </opcode>
+ <opcode> DB /mod=11 /x87=0C ; ST0 ST4 </opcode>
+ <opcode> DB /mod=11 /x87=0D ; ST0 ST5 </opcode>
+ <opcode> DB /mod=11 /x87=0E ; ST0 ST6 </opcode>
+ <opcode> DB /mod=11 /x87=0F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcmovnbe">
+ <opcode> DB /mod=11 /x87=10 ; ST0 ST0 </opcode>
+ <opcode> DB /mod=11 /x87=11 ; ST0 ST1 </opcode>
+ <opcode> DB /mod=11 /x87=12 ; ST0 ST2 </opcode>
+ <opcode> DB /mod=11 /x87=13 ; ST0 ST3 </opcode>
+ <opcode> DB /mod=11 /x87=14 ; ST0 ST4 </opcode>
+ <opcode> DB /mod=11 /x87=15 ; ST0 ST5 </opcode>
+ <opcode> DB /mod=11 /x87=16 ; ST0 ST6 </opcode>
+ <opcode> DB /mod=11 /x87=17 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcmovnu">
+ <opcode> DB /mod=11 /x87=18 ; ST0 ST0 </opcode>
+ <opcode> DB /mod=11 /x87=19 ; ST0 ST1 </opcode>
+ <opcode> DB /mod=11 /x87=1A ; ST0 ST2 </opcode>
+ <opcode> DB /mod=11 /x87=1B ; ST0 ST3 </opcode>
+ <opcode> DB /mod=11 /x87=1C ; ST0 ST4 </opcode>
+ <opcode> DB /mod=11 /x87=1D ; ST0 ST5 </opcode>
+ <opcode> DB /mod=11 /x87=1E ; ST0 ST6 </opcode>
+ <opcode> DB /mod=11 /x87=1F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fucomi">
+ <opcode> DB /mod=11 /x87=28 ; ST0 ST0 </opcode>
+ <opcode> DB /mod=11 /x87=29 ; ST0 ST1 </opcode>
+ <opcode> DB /mod=11 /x87=2A ; ST0 ST2 </opcode>
+ <opcode> DB /mod=11 /x87=2B ; ST0 ST3 </opcode>
+ <opcode> DB /mod=11 /x87=2C ; ST0 ST4 </opcode>
+ <opcode> DB /mod=11 /x87=2D ; ST0 ST5 </opcode>
+ <opcode> DB /mod=11 /x87=2E ; ST0 ST6 </opcode>
+ <opcode> DB /mod=11 /x87=2F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcom">
+ <opcode cast="1"> aso rexr rexx rexb ; D8 /mod=!11 /2 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DC /mod=!11 /2 ; Mq </opcode>
+ <opcode> D8 /mod=11 /x87=10 ; ST0 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=11 ; ST0 ST1 </opcode>
+ <opcode> D8 /mod=11 /x87=12 ; ST0 ST2 </opcode>
+ <opcode> D8 /mod=11 /x87=13 ; ST0 ST3 </opcode>
+ <opcode> D8 /mod=11 /x87=14 ; ST0 ST4 </opcode>
+ <opcode> D8 /mod=11 /x87=15 ; ST0 ST5 </opcode>
+ <opcode> D8 /mod=11 /x87=16 ; ST0 ST6 </opcode>
+ <opcode> D8 /mod=11 /x87=17 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcom2">
+ <opcode> DC /mod=11 /x87=10 ; ST0 </opcode>
+ <opcode> DC /mod=11 /x87=11 ; ST1 </opcode>
+ <opcode> DC /mod=11 /x87=12 ; ST2 </opcode>
+ <opcode> DC /mod=11 /x87=13 ; ST3 </opcode>
+ <opcode> DC /mod=11 /x87=14 ; ST4 </opcode>
+ <opcode> DC /mod=11 /x87=15 ; ST5 </opcode>
+ <opcode> DC /mod=11 /x87=16 ; ST6 </opcode>
+ <opcode> DC /mod=11 /x87=17 ; ST7 </opcode>
+ <class> X87 UNDOC </class>
+ </instruction>
+
+ <instruction mnemonic="fcomp3">
+ <opcode> DC /mod=11 /x87=18 ; ST0 </opcode>
+ <opcode> DC /mod=11 /x87=19 ; ST1 </opcode>
+ <opcode> DC /mod=11 /x87=1A ; ST2 </opcode>
+ <opcode> DC /mod=11 /x87=1B ; ST3 </opcode>
+ <opcode> DC /mod=11 /x87=1C ; ST4 </opcode>
+ <opcode> DC /mod=11 /x87=1D ; ST5 </opcode>
+ <opcode> DC /mod=11 /x87=1E ; ST6 </opcode>
+ <opcode> DC /mod=11 /x87=1F ; ST7 </opcode>
+ <class> X87 UNDOC </class>
+ </instruction>
+
+ <instruction mnemonic="fcomi">
+ <opcode> DB /mod=11 /x87=30 ; ST0 ST0 </opcode>
+ <opcode> DB /mod=11 /x87=31 ; ST0 ST1 </opcode>
+ <opcode> DB /mod=11 /x87=32 ; ST0 ST2 </opcode>
+ <opcode> DB /mod=11 /x87=33 ; ST0 ST3 </opcode>
+ <opcode> DB /mod=11 /x87=34 ; ST0 ST4 </opcode>
+ <opcode> DB /mod=11 /x87=35 ; ST0 ST5 </opcode>
+ <opcode> DB /mod=11 /x87=36 ; ST0 ST6 </opcode>
+ <opcode> DB /mod=11 /x87=37 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fucomip">
+ <opcode> DF /mod=11 /x87=28 ; ST0 ST0 </opcode>
+ <opcode> DF /mod=11 /x87=29 ; ST0 ST1 </opcode>
+ <opcode> DF /mod=11 /x87=2A ; ST0 ST2 </opcode>
+ <opcode> DF /mod=11 /x87=2B ; ST0 ST3 </opcode>
+ <opcode> DF /mod=11 /x87=2C ; ST0 ST4 </opcode>
+ <opcode> DF /mod=11 /x87=2D ; ST0 ST5 </opcode>
+ <opcode> DF /mod=11 /x87=2E ; ST0 ST6 </opcode>
+ <opcode> DF /mod=11 /x87=2F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcomip">
+ <opcode> DF /mod=11 /x87=30 ; ST0 ST0 </opcode>
+ <opcode> DF /mod=11 /x87=31 ; ST0 ST1 </opcode>
+ <opcode> DF /mod=11 /x87=32 ; ST0 ST2 </opcode>
+ <opcode> DF /mod=11 /x87=33 ; ST0 ST3 </opcode>
+ <opcode> DF /mod=11 /x87=34 ; ST0 ST4 </opcode>
+ <opcode> DF /mod=11 /x87=35 ; ST0 ST5 </opcode>
+ <opcode> DF /mod=11 /x87=36 ; ST0 ST6 </opcode>
+ <opcode> DF /mod=11 /x87=37 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcomp">
+ <opcode cast="1"> aso rexr rexx rexb ; D8 /mod=!11 /3 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DC /mod=!11 /3 ; Mq </opcode>
+ <opcode> D8 /mod=11 /x87=18 ; ST0 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=19 ; ST0 ST1 </opcode>
+ <opcode> D8 /mod=11 /x87=1A ; ST0 ST2 </opcode>
+ <opcode> D8 /mod=11 /x87=1B ; ST0 ST3 </opcode>
+ <opcode> D8 /mod=11 /x87=1C ; ST0 ST4 </opcode>
+ <opcode> D8 /mod=11 /x87=1D ; ST0 ST5 </opcode>
+ <opcode> D8 /mod=11 /x87=1E ; ST0 ST6 </opcode>
+ <opcode> D8 /mod=11 /x87=1F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcomp5">
+ <opcode> DE /mod=11 /x87=10 ; ST0 </opcode>
+ <opcode> DE /mod=11 /x87=11 ; ST1 </opcode>
+ <opcode> DE /mod=11 /x87=12 ; ST2 </opcode>
+ <opcode> DE /mod=11 /x87=13 ; ST3 </opcode>
+ <opcode> DE /mod=11 /x87=14 ; ST4 </opcode>
+ <opcode> DE /mod=11 /x87=15 ; ST5 </opcode>
+ <opcode> DE /mod=11 /x87=16 ; ST6 </opcode>
+ <opcode> DE /mod=11 /x87=17 ; ST7 </opcode>
+ <class> X87 UNDOC </class>
+ </instruction>
+
+ <instruction mnemonic="fcompp">
+ <opcode> DE /mod=11 /x87=19 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fcos">
+ <opcode> D9 /mod=11 /x87=3F ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fdecstp">
+ <opcode> D9 /mod=11 /x87=36 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fdiv">
+ <opcode cast="1"> aso rexr rexx rexb ; DC /mod=!11 /6 ; Mq </opcode>
+ <opcode> DC /mod=11 /x87=38 ; ST0 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=39 ; ST1 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=3A ; ST2 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=3B ; ST3 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=3C ; ST4 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=3D ; ST5 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=3E ; ST6 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=3F ; ST7 ST0 </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; D8 /mod=!11 /6 ; Md </opcode>
+ <opcode> D8 /mod=11 /x87=30 ; ST0 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=31 ; ST0 ST1 </opcode>
+ <opcode> D8 /mod=11 /x87=32 ; ST0 ST2 </opcode>
+ <opcode> D8 /mod=11 /x87=33 ; ST0 ST3 </opcode>
+ <opcode> D8 /mod=11 /x87=34 ; ST0 ST4 </opcode>
+ <opcode> D8 /mod=11 /x87=35 ; ST0 ST5 </opcode>
+ <opcode> D8 /mod=11 /x87=36 ; ST0 ST6 </opcode>
+ <opcode> D8 /mod=11 /x87=37 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fdivp">
+ <opcode> DE /mod=11 /x87=38 ; ST0 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=39 ; ST1 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=3A ; ST2 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=3B ; ST3 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=3C ; ST4 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=3D ; ST5 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=3E ; ST6 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=3F ; ST7 ST0 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fdivr">
+ <opcode cast="1"> aso rexr rexx rexb ; DC /mod=!11 /7 ; Mq </opcode>
+ <opcode> DC /mod=11 /x87=30 ; ST0 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=31 ; ST1 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=32 ; ST2 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=33 ; ST3 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=34 ; ST4 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=35 ; ST5 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=36 ; ST6 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=37 ; ST7 ST0 </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; D8 /mod=!11 /7 ; Md </opcode>
+ <opcode> D8 /mod=11 /x87=38 ; ST0 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=39 ; ST0 ST1 </opcode>
+ <opcode> D8 /mod=11 /x87=3A ; ST0 ST2 </opcode>
+ <opcode> D8 /mod=11 /x87=3B ; ST0 ST3 </opcode>
+ <opcode> D8 /mod=11 /x87=3C ; ST0 ST4 </opcode>
+ <opcode> D8 /mod=11 /x87=3D ; ST0 ST5 </opcode>
+ <opcode> D8 /mod=11 /x87=3E ; ST0 ST6 </opcode>
+ <opcode> D8 /mod=11 /x87=3F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fdivrp">
+ <opcode> DE /mod=11 /x87=30 ; ST0 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=31 ; ST1 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=32 ; ST2 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=33 ; ST3 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=34 ; ST4 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=35 ; ST5 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=36 ; ST6 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=37 ; ST7 ST0 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="femms">
+ <opcode> 0f 0e ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="ffree">
+ <opcode> DD /mod=11 /x87=00 ; ST0 </opcode>
+ <opcode> DD /mod=11 /x87=01 ; ST1 </opcode>
+ <opcode> DD /mod=11 /x87=02 ; ST2 </opcode>
+ <opcode> DD /mod=11 /x87=03 ; ST3 </opcode>
+ <opcode> DD /mod=11 /x87=04 ; ST4 </opcode>
+ <opcode> DD /mod=11 /x87=05 ; ST5 </opcode>
+ <opcode> DD /mod=11 /x87=06 ; ST6 </opcode>
+ <opcode> DD /mod=11 /x87=07 ; ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="ffreep">
+ <opcode> DF /mod=11 /x87=00 ; ST0 </opcode>
+ <opcode> DF /mod=11 /x87=01 ; ST1 </opcode>
+ <opcode> DF /mod=11 /x87=02 ; ST2 </opcode>
+ <opcode> DF /mod=11 /x87=03 ; ST3 </opcode>
+ <opcode> DF /mod=11 /x87=04 ; ST4 </opcode>
+ <opcode> DF /mod=11 /x87=05 ; ST5 </opcode>
+ <opcode> DF /mod=11 /x87=06 ; ST6 </opcode>
+ <opcode> DF /mod=11 /x87=07 ; ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="ficom">
+ <opcode cast="1"> aso rexr rexx rexb ; DE /mod=!11 /2 ; Mw </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DA /mod=!11 /2 ; Md </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="ficomp">
+ <opcode cast="1"> aso rexr rexx rexb ; DE /mod=!11 /3 ; Mw </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DA /mod=!11 /3 ; Md </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fild">
+ <opcode cast="1"> aso rexr rexx rexb ; DF /mod=!11 /0 ; Mw </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DF /mod=!11 /5 ; Mq </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DB /mod=!11 /0 ; Md </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fncstp">
+ <opcode> D9 /mod=11 /x87=37 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fninit">
+ <opcode> DB /mod=11 /x87=23 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fiadd">
+ <opcode cast="1"> aso rexr rexx rexb ; DA /mod=!11 /0 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DE /mod=!11 /0 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fidivr">
+ <opcode cast="1"> aso rexr rexx rexb ; DA /mod=!11 /7 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DE /mod=!11 /7 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fidiv">
+ <opcode cast="1"> aso rexr rexx rexb ; DA /mod=!11 /6 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DE /mod=!11 /6 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fisub">
+ <opcode cast="1"> aso rexr rexx rexb ; DA /mod=!11 /4 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DE /mod=!11 /4 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fisubr">
+ <opcode cast="1"> aso rexr rexx rexb ; DA /mod=!11 /5 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DE /mod=!11 /5 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fist">
+ <opcode cast="1"> aso rexr rexx rexb ; DF /mod=!11 /2 ; Mw </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DB /mod=!11 /2 ; Md </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fistp">
+ <opcode cast="1"> aso rexr rexx rexb ; DF /mod=!11 /3 ; Mw </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DF /mod=!11 /7 ; Mq </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DB /mod=!11 /3 ; Md </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fisttp">
+ <opcode cast="1"> aso rexr rexx rexb ; DB /mod=!11 /1 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DD /mod=!11 /1 ; Mq </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DF /mod=!11 /1 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fld">
+ <opcode cast="1"> aso rexr rexx rexb ; DB /mod=!11 /5 ; Mt </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DD /mod=!11 /0 ; Mq </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; D9 /mod=!11 /0 ; Md </opcode>
+ <opcode> D9 /mod=11 /x87=00 ; ST0 ST0 </opcode>
+ <opcode> D9 /mod=11 /x87=01 ; ST0 ST1 </opcode>
+ <opcode> D9 /mod=11 /x87=02 ; ST0 ST2 </opcode>
+ <opcode> D9 /mod=11 /x87=03 ; ST0 ST3 </opcode>
+ <opcode> D9 /mod=11 /x87=04 ; ST0 ST4 </opcode>
+ <opcode> D9 /mod=11 /x87=05 ; ST0 ST5 </opcode>
+ <opcode> D9 /mod=11 /x87=06 ; ST0 ST6 </opcode>
+ <opcode> D9 /mod=11 /x87=07 ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fld1">
+ <opcode> D9 /mod=11 /x87=28 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fldl2t">
+ <opcode> D9 /mod=11 /x87=29 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fldl2e">
+ <opcode> D9 /mod=11 /x87=2A ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fldlpi">
+ <opcode> D9 /mod=11 /x87=2B ;</opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fldlg2">
+ <opcode> D9 /mod=11 /x87=2C ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fldln2">
+ <opcode> D9 /mod=11 /x87=2D ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fldz">
+ <opcode> D9 /mod=11 /x87=2E ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fldcw">
+ <opcode cast="1"> aso rexr rexx rexb ; D9 /mod=!11 /5 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fldenv">
+ <opcode> aso rexr rexx rexb ; D9 /mod=!11 /4 ; M </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fmul">
+ <opcode cast="1"> aso rexr rexx rexb ; DC /mod=!11 /1 ; Mq </opcode>
+ <opcode> DC /mod=11 /x87=08 ; ST0 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=09 ; ST1 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=0A ; ST2 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=0B ; ST3 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=0C ; ST4 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=0D ; ST5 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=0E ; ST6 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=0F ; ST7 ST0 </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; D8 /mod=!11 /1 ; Md </opcode>
+ <opcode> D8 /mod=11 /x87=08 ; ST0 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=09 ; ST0 ST1 </opcode>
+ <opcode> D8 /mod=11 /x87=0A ; ST0 ST2 </opcode>
+ <opcode> D8 /mod=11 /x87=0B ; ST0 ST3 </opcode>
+ <opcode> D8 /mod=11 /x87=0C ; ST0 ST4 </opcode>
+ <opcode> D8 /mod=11 /x87=0D ; ST0 ST5 </opcode>
+ <opcode> D8 /mod=11 /x87=0E ; ST0 ST6 </opcode>
+ <opcode> D8 /mod=11 /x87=0F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fmulp">
+ <opcode> DE /mod=11 /x87=08 ; ST0 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=09 ; ST1 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=0A ; ST2 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=0B ; ST3 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=0C ; ST4 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=0D ; ST5 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=0E ; ST6 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=0F ; ST7 ST0 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fimul">
+ <opcode cast="1"> aso rexr rexx rexb ; DA /mod=!11 /1 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DE /mod=!11 /1 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fnop">
+ <opcode> D9 /mod=11 /x87=10 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fpatan">
+ <opcode> D9 /mod=11 /x87=33 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fprem">
+ <opcode> D9 /mod=11 /x87=38 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fprem1">
+ <opcode> D9 /mod=11 /x87=35 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fptan">
+ <opcode> D9 /mod=11 /x87=32 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="frndint">
+ <opcode> D9 /mod=11 /x87=3C ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="frstor">
+ <opcode> aso rexr rexx rexb ; DD /mod=!11 /4 ; M </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fnsave">
+ <opcode> aso rexr rexx rexb ; DD /mod=!11 /6 ; M </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fscale">
+ <opcode> D9 /mod=11 /x87=3D ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fsin">
+ <opcode> D9 /mod=11 /x87=3E ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fsincos">
+ <opcode> D9 /mod=11 /x87=3B ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fsqrt">
+ <opcode> D9 /mod=11 /x87=3A ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fstp">
+ <opcode cast="1"> aso rexr rexx rexb ; DB /mod=!11 /7 ; Mt </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DD /mod=!11 /3 ; Mq </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; D9 /mod=!11 /3 ; Md </opcode>
+ <opcode> DD /mod=11 /x87=18 ; ST0 </opcode>
+ <opcode> DD /mod=11 /x87=19 ; ST1 </opcode>
+ <opcode> DD /mod=11 /x87=1A ; ST2 </opcode>
+ <opcode> DD /mod=11 /x87=1B ; ST3 </opcode>
+ <opcode> DD /mod=11 /x87=1C ; ST4 </opcode>
+ <opcode> DD /mod=11 /x87=1D ; ST5 </opcode>
+ <opcode> DD /mod=11 /x87=1E ; ST6 </opcode>
+ <opcode> DD /mod=11 /x87=1F ; ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fstp1">
+ <opcode> D9 /mod=11 /x87=18 ; ST0 </opcode>
+ <opcode> D9 /mod=11 /x87=19 ; ST1 </opcode>
+ <opcode> D9 /mod=11 /x87=1A ; ST2 </opcode>
+ <opcode> D9 /mod=11 /x87=1B ; ST3 </opcode>
+ <opcode> D9 /mod=11 /x87=1C ; ST4 </opcode>
+ <opcode> D9 /mod=11 /x87=1D ; ST5 </opcode>
+ <opcode> D9 /mod=11 /x87=1E ; ST6 </opcode>
+ <opcode> D9 /mod=11 /x87=1F ; ST7 </opcode>
+ </instruction>
+
+ <instruction mnemonic="fstp8">
+ <opcode> DF /mod=11 /x87=10 ; ST0 </opcode>
+ <opcode> DF /mod=11 /x87=11 ; ST1 </opcode>
+ <opcode> DF /mod=11 /x87=12 ; ST2 </opcode>
+ <opcode> DF /mod=11 /x87=13 ; ST3 </opcode>
+ <opcode> DF /mod=11 /x87=14 ; ST4 </opcode>
+ <opcode> DF /mod=11 /x87=15 ; ST5 </opcode>
+ <opcode> DF /mod=11 /x87=16 ; ST6 </opcode>
+ <opcode> DF /mod=11 /x87=17 ; ST7 </opcode>
+ </instruction>
+
+ <instruction mnemonic="fstp9">
+ <opcode> DF /mod=11 /x87=18 ; ST0 </opcode>
+ <opcode> DF /mod=11 /x87=19 ; ST1 </opcode>
+ <opcode> DF /mod=11 /x87=1A ; ST2 </opcode>
+ <opcode> DF /mod=11 /x87=1B ; ST3 </opcode>
+ <opcode> DF /mod=11 /x87=1C ; ST4 </opcode>
+ <opcode> DF /mod=11 /x87=1D ; ST5 </opcode>
+ <opcode> DF /mod=11 /x87=1E ; ST6 </opcode>
+ <opcode> DF /mod=11 /x87=1F ; ST7 </opcode>
+ </instruction>
+
+ <instruction mnemonic="fst">
+ <opcode cast="1"> aso rexr rexx rexb ; D9 /mod=!11 /2 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DD /mod=!11 /2 ; Mq </opcode>
+ <opcode> DD /mod=11 /x87=10 ; ST0 </opcode>
+ <opcode> DD /mod=11 /x87=11 ; ST1 </opcode>
+ <opcode> DD /mod=11 /x87=12 ; ST2 </opcode>
+ <opcode> DD /mod=11 /x87=13 ; ST3 </opcode>
+ <opcode> DD /mod=11 /x87=14 ; ST4 </opcode>
+ <opcode> DD /mod=11 /x87=15 ; ST5 </opcode>
+ <opcode> DD /mod=11 /x87=16 ; ST6 </opcode>
+ <opcode> DD /mod=11 /x87=17 ; ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fnstcw">
+ <opcode cast="1"> aso rexr rexx rexb ; D9 /mod=!11 /7 ; Mw </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fnstenv">
+ <opcode> aso rexr rexx rexb ; D9 /mod=!11 /6 ; M </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fnstsw">
+ <opcode cast="1"> aso rexr rexx rexb ; DD /mod=!11 /7 ; Mw </opcode>
+ <opcode> DF /mod=11 /x87=20 ; AX </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fsub">
+ <opcode cast="1"> aso rexr rexx rexb ; D8 /mod=!11 /4 ; Md </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; DC /mod=!11 /4 ; Mq </opcode>
+ <opcode> D8 /mod=11 /x87=20 ; ST0 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=21 ; ST0 ST1 </opcode>
+ <opcode> D8 /mod=11 /x87=22 ; ST0 ST2 </opcode>
+ <opcode> D8 /mod=11 /x87=23 ; ST0 ST3 </opcode>
+ <opcode> D8 /mod=11 /x87=24 ; ST0 ST4 </opcode>
+ <opcode> D8 /mod=11 /x87=25 ; ST0 ST5 </opcode>
+ <opcode> D8 /mod=11 /x87=26 ; ST0 ST6 </opcode>
+ <opcode> D8 /mod=11 /x87=27 ; ST0 ST7 </opcode>
+ <opcode> DC /mod=11 /x87=28 ; ST0 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=29 ; ST1 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=2A ; ST2 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=2B ; ST3 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=2C ; ST4 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=2D ; ST5 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=2E ; ST6 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=2F ; ST7 ST0 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fsubp">
+ <opcode> DE /mod=11 /x87=28 ; ST0 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=29 ; ST1 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=2A ; ST2 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=2B ; ST3 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=2C ; ST4 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=2D ; ST5 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=2E ; ST6 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=2F ; ST7 ST0 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fsubr">
+ <opcode cast="1"> aso rexr rexx rexb ; DC /mod=!11 /5 ; Mq </opcode>
+ <opcode> D8 /mod=11 /x87=28 ; ST0 ST0 </opcode>
+ <opcode> D8 /mod=11 /x87=29 ; ST0 ST1 </opcode>
+ <opcode> D8 /mod=11 /x87=2A ; ST0 ST2 </opcode>
+ <opcode> D8 /mod=11 /x87=2B ; ST0 ST3 </opcode>
+ <opcode> D8 /mod=11 /x87=2C ; ST0 ST4 </opcode>
+ <opcode> D8 /mod=11 /x87=2D ; ST0 ST5 </opcode>
+ <opcode> D8 /mod=11 /x87=2E ; ST0 ST6 </opcode>
+ <opcode> D8 /mod=11 /x87=2F ; ST0 ST7 </opcode>
+ <opcode> DC /mod=11 /x87=20 ; ST0 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=21 ; ST1 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=22 ; ST2 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=23 ; ST3 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=24 ; ST4 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=25 ; ST5 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=26 ; ST6 ST0 </opcode>
+ <opcode> DC /mod=11 /x87=27 ; ST7 ST0 </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; D8 /mod=!11 /5 ; Md </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fsubrp">
+ <opcode> DE /mod=11 /x87=20 ; ST0 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=21 ; ST1 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=22 ; ST2 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=23 ; ST3 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=24 ; ST4 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=25 ; ST5 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=26 ; ST6 ST0 </opcode>
+ <opcode> DE /mod=11 /x87=27 ; ST7 ST0 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="ftst">
+ <opcode> D9 /mod=11 /x87=24 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fucom">
+ <opcode> DD /mod=11 /x87=20 ; ST0 </opcode>
+ <opcode> DD /mod=11 /x87=21 ; ST1 </opcode>
+ <opcode> DD /mod=11 /x87=22 ; ST2 </opcode>
+ <opcode> DD /mod=11 /x87=23 ; ST3 </opcode>
+ <opcode> DD /mod=11 /x87=24 ; ST4 </opcode>
+ <opcode> DD /mod=11 /x87=25 ; ST5 </opcode>
+ <opcode> DD /mod=11 /x87=26 ; ST6 </opcode>
+ <opcode> DD /mod=11 /x87=27 ; ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fucomp">
+ <opcode> DD /mod=11 /x87=28 ; ST0 </opcode>
+ <opcode> DD /mod=11 /x87=29 ; ST1 </opcode>
+ <opcode> DD /mod=11 /x87=2A ; ST2 </opcode>
+ <opcode> DD /mod=11 /x87=2B ; ST3 </opcode>
+ <opcode> DD /mod=11 /x87=2C ; ST4 </opcode>
+ <opcode> DD /mod=11 /x87=2D ; ST5 </opcode>
+ <opcode> DD /mod=11 /x87=2E ; ST6 </opcode>
+ <opcode> DD /mod=11 /x87=2F ; ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fucompp">
+ <opcode> DA /mod=11 /x87=29 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fxam">
+ <opcode> D9 /mod=11 /x87=25 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fxch">
+ <opcode> D9 /mod=11 /x87=08 ; ST0 ST0 </opcode>
+ <opcode> D9 /mod=11 /x87=09 ; ST0 ST1 </opcode>
+ <opcode> D9 /mod=11 /x87=0A ; ST0 ST2 </opcode>
+ <opcode> D9 /mod=11 /x87=0B ; ST0 ST3 </opcode>
+ <opcode> D9 /mod=11 /x87=0C ; ST0 ST4 </opcode>
+ <opcode> D9 /mod=11 /x87=0D ; ST0 ST5 </opcode>
+ <opcode> D9 /mod=11 /x87=0E ; ST0 ST6 </opcode>
+ <opcode> D9 /mod=11 /x87=0F ; ST0 ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fxch4">
+ <opcode> DD /mod=11 /x87=08 ; ST0 </opcode>
+ <opcode> DD /mod=11 /x87=09 ; ST1 </opcode>
+ <opcode> DD /mod=11 /x87=0A ; ST2 </opcode>
+ <opcode> DD /mod=11 /x87=0B ; ST3 </opcode>
+ <opcode> DD /mod=11 /x87=0C ; ST4 </opcode>
+ <opcode> DD /mod=11 /x87=0D ; ST5 </opcode>
+ <opcode> DD /mod=11 /x87=0E ; ST6 </opcode>
+ <opcode> DD /mod=11 /x87=0F ; ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fxch7">
+ <opcode> DF /mod=11 /x87=08 ; ST0 </opcode>
+ <opcode> DF /mod=11 /x87=09 ; ST1 </opcode>
+ <opcode> DF /mod=11 /x87=0A ; ST2 </opcode>
+ <opcode> DF /mod=11 /x87=0B ; ST3 </opcode>
+ <opcode> DF /mod=11 /x87=0C ; ST4 </opcode>
+ <opcode> DF /mod=11 /x87=0D ; ST5 </opcode>
+ <opcode> DF /mod=11 /x87=0E ; ST6 </opcode>
+ <opcode> DF /mod=11 /x87=0F ; ST7 </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fxrstor">
+ <opcode> aso rexw rexr rexx rexb ; 0F AE /1 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="fxsave">
+ <opcode> aso rexw rexr rexx rexb ; 0F AE /0 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="fpxtract">
+ <opcode> D9 /mod=11 /x87=34 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fyl2x">
+ <opcode> D9 /mod=11 /x87=31 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="fyl2xp1">
+ <opcode> D9 /mod=11 /x87=39 ; </opcode>
+ <class> X87 </class>
+ </instruction>
+
+ <instruction mnemonic="haddpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 7c ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="haddps">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 7c ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="hlt">
+ <opcode> f4 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="hsubpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 7d ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="hsubps">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 7d ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="idiv">
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; F7 /7 ; Ev </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; F6 /7 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="in">
+ <opcode> ; e4 ; AL Ib </opcode>
+ <opcode> oso ; e5 ; eAX Ib </opcode>
+ <opcode> ec ; AL DX </opcode>
+ <opcode> oso ; ed ; eAX DX </opcode>
+ </instruction>
+
+ <instruction mnemonic="imul">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f af ; Gv Ev </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; F6 /5 ; Eb </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; F7 /5 ; Ev </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 69 ; Gv Ev Iz </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 6b ; Gv Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="inc">
+ <opcode> oso ; 40 ; eAX </opcode>
+ <opcode> oso ; 41 ; eCX </opcode>
+ <opcode> oso ; 42 ; eDX </opcode>
+ <opcode> oso ; 43 ; eBX </opcode>
+ <opcode> oso ; 44 ; eSP </opcode>
+ <opcode> oso ; 45 ; eBP </opcode>
+ <opcode> oso ; 46 ; eSI </opcode>
+ <opcode> oso ; 47 ; eDI </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; FF /0 ; Ev </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; FE /0 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="insb">
+ <opcode> ; 6c ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="insw">
+ <opcode> oso ; 6d /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="insd">
+ <opcode> oso ; 6d /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="int1">
+ <opcode> f1 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="int3">
+ <opcode> ; cc ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="int">
+ <opcode> ; cd ; Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="into">
+ <opcode mode="inv64"> ; ce ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="invd">
+ <opcode> 0f 08 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="invept">
+ <opcode> sse66 0f 38 80 /M32 ; Gd Mo </opcode>
+ <opcode> sse66 0f 38 80 /M64 ; Gq Mo </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="invlpg">
+ <opcode> aso rexr rexx rexb ; 0F 01 /7 /mod=!11 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="invlpga">
+ <opcode> 0F 01 /3 /mod=11 /rm=7 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="invvpid">
+ <opcode> sse66 0f 38 81 /M32 ; Gd Mo </opcode>
+ <opcode> sse66 0f 38 81 /M64 ; Gq Mo </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="iretw">
+ <opcode> oso rexw ; cf /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="iretd">
+ <opcode> oso rexw ; cf /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="iretq">
+ <opcode> oso rexw ; cf /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="jo">
+ <opcode> ; 70 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 80 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jno">
+ <opcode> ; 71 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 81 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jb">
+ <opcode> ; 72 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 82 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jae">
+ <opcode> ; 73 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 83 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jz">
+ <opcode> ; 74 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 84 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jnz">
+ <opcode> ; 75 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 85 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jbe">
+ <opcode> ; 76 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 86 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="ja">
+ <opcode> ; 77 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 87 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="js">
+ <opcode> ; 78 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 88 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jns">
+ <opcode> ; 79 ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 89 ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jp">
+ <opcode> ; 7a ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 8a ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jnp">
+ <opcode> ; 7b ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 8b ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jl">
+ <opcode> ; 7c ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 8c ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jge">
+ <opcode> ; 7d ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 8d ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jle">
+ <opcode> ; 7e ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 8e ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jg">
+ <opcode> ; 7f ; Jb </opcode>
+ <opcode mode="def64 depM" cast="1"> oso ; 0f 8f ; Jz </opcode>
+ </instruction>
+
+ <instruction mnemonic="jcxz">
+ <opcode> aso ; e3 /A16 ; Jb </opcode>
+ </instruction>
+
+ <instruction mnemonic="jecxz">
+ <opcode> aso ; e3 /A32 ; Jb </opcode>
+ </instruction>
+
+ <instruction mnemonic="jrcxz">
+ <opcode> aso ; e3 /A64 ; Jb </opcode>
+ </instruction>
+
+ <instruction mnemonic="jmp">
+ <opcode mode="def64 depM" cast="1"> aso oso rexw rexr rexx rexb ; FF /4 ; Ev </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; FF /5 ; Ep </opcode>
+ <opcode mode="def64 depM"> oso ; e9 ; Jz </opcode>
+ <opcode mode="inv64"> ea ; Ap </opcode>
+ <opcode> eb ; Jb </opcode>
+ </instruction>
+
+ <instruction mnemonic="lahf">
+ <opcode> ; 9f ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="lar">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 02 ; Gv Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="lddqu">
+ <opcode> aso rexr rexx rexb ; ssef2 0f f0 ; V M </opcode>
+ </instruction>
+
+ <instruction mnemonic="ldmxcsr">
+ <opcode> aso rexw rexr rexx rexb ; 0F AE /2 ; Md </opcode>
+ </instruction>
+
+ <instruction mnemonic="lds">
+ <opcode mode="inv64"> aso oso ; c5 ; Gv M </opcode>
+ </instruction>
+
+ <instruction mnemonic="lea">
+ <opcode> aso oso rexw rexr rexx rexb ; 8d ; Gv M </opcode>
+ </instruction>
+
+ <instruction mnemonic="les">
+ <opcode mode="inv64"> aso oso ; c4 ; Gv M </opcode>
+ </instruction>
+
+ <instruction mnemonic="lfs">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f b4 ; Gz M </opcode>
+ </instruction>
+
+ <instruction mnemonic="lgs">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f b5 ; Gz M </opcode>
+ </instruction>
+
+ <instruction mnemonic="lidt">
+ <opcode> aso rexr rexx rexb ; 0F 01 /3 /mod=!11 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="lss">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f b2 ; Gz M </opcode>
+ </instruction>
+
+ <instruction mnemonic="leave">
+ <opcode> ; c9 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="lfence">
+ <opcode> 0F AE /5 /mod=11 /rm=0 ; </opcode>
+ <opcode> 0F AE /5 /mod=11 /rm=1 ; </opcode>
+ <opcode> 0F AE /5 /mod=11 /rm=2 ; </opcode>
+ <opcode> 0F AE /5 /mod=11 /rm=3 ; </opcode>
+ <opcode> 0F AE /5 /mod=11 /rm=4 ; </opcode>
+ <opcode> 0F AE /5 /mod=11 /rm=5 ; </opcode>
+ <opcode> 0F AE /5 /mod=11 /rm=6 ; </opcode>
+ <opcode> 0F AE /5 /mod=11 /rm=7 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="lgdt">
+ <opcode> aso rexr rexx rexb ; 0F 01 /2 /mod=!11 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="lldt">
+ <opcode> aso rexr rexx rexb ; 0F 00 /2 ; Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="lmsw">
+ <opcode> aso rexr rexx rexb ; 0F 01 /6 /mod=!11 ; Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="lock">
+ <opcode> f0 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="lodsb">
+ <opcode imp_addr="1"> ; ac ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="lodsw">
+ <opcode imp_addr="1"> oso rexw ; ad /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="lodsd">
+ <opcode imp_addr="1"> oso rexw ; ad /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="lodsq">
+ <opcode imp_addr="1"> oso rexw ; ad /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="loopnz">
+ <opcode> ; e0 ; Jb </opcode>
+ </instruction>
+
+ <instruction mnemonic="loope">
+ <opcode> ; e1 ; Jb </opcode>
+ </instruction>
+
+ <instruction mnemonic="loop">
+ <opcode> ; e2 ; Jb </opcode>
+ <mode> def64 depM </mode>
+ </instruction>
+
+ <instruction mnemonic="lsl">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f 03 ; Gv Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="ltr">
+ <opcode> aso rexr rexx rexb ; 0F 00 /3 ; Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="maskmovq">
+ <opcode> aso rexr rexx rexb ; 0f f7 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f f7 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="maxpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 5f ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="maxps">
+ <opcode> aso rexr rexx rexb ; 0f 5f ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="maxsd">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 5f ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="maxss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 5f ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="mfence">
+ <opcode> 0F AE /6 /mod=11 /rm=0 ; </opcode>
+ <opcode> 0F AE /6 /mod=11 /rm=1 ; </opcode>
+ <opcode> 0F AE /6 /mod=11 /rm=2 ; </opcode>
+ <opcode> 0F AE /6 /mod=11 /rm=3 ; </opcode>
+ <opcode> 0F AE /6 /mod=11 /rm=4 ; </opcode>
+ <opcode> 0F AE /6 /mod=11 /rm=5 ; </opcode>
+ <opcode> 0F AE /6 /mod=11 /rm=6 ; </opcode>
+ <opcode> 0F AE /6 /mod=11 /rm=7 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="minpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 5d ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="minps">
+ <opcode> aso rexr rexx rexb ; 0f 5d ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="minsd">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 5d ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="minss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 5d ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="monitor">
+ <opcode> 0F 01 /1 /mod=11 /rm=0 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="montmul">
+ <opcode> ; 0f a6 /mod=11 /rm=0 /0 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="mov">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C6 /0 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C7 /0 ; Ev Iz </opcode>
+ <opcode> aso rexr rexx rexb ; 88 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 89 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 8a ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 8b ; Gv Ev </opcode>
+ <opcode> aso oso rexr rexx rexb ; 8c ; Ev S </opcode>
+ <opcode> aso oso rexr rexx rexb ; 8e ; S Ev </opcode>
+ <opcode> a0 ; AL Ob </opcode>
+ <opcode> aso oso rexw ; a1 ; rAX Ov </opcode>
+ <opcode> a2 ; Ob AL </opcode>
+ <opcode> aso oso rexw ; a3 ; Ov rAX </opcode>
+ <opcode> rexb ; b0 ; ALr8b Ib </opcode>
+ <opcode> rexb ; b1 ; CLr9b Ib </opcode>
+ <opcode> rexb ; b2 ; DLr10b Ib </opcode>
+ <opcode> rexb ; b3 ; BLr11b Ib </opcode>
+ <opcode> rexb ; b4 ; AHr12b Ib </opcode>
+ <opcode> rexb ; b5 ; CHr13b Ib </opcode>
+ <opcode> rexb ; b6 ; DHr14b Ib </opcode>
+ <opcode> rexb ; b7 ; BHr15b Ib </opcode>
+ <opcode> oso rexw rexb ; b8 ; rAXr8 Iv </opcode>
+ <opcode> oso rexw rexb ; b9 ; rCXr9 Iv </opcode>
+ <opcode> oso rexw rexb ; ba ; rDXr10 Iv </opcode>
+ <opcode> oso rexw rexb ; bb ; rBXr11 Iv </opcode>
+ <opcode> oso rexw rexb ; bc ; rSPr12 Iv </opcode>
+ <opcode> oso rexw rexb ; bd ; rBPr13 Iv </opcode>
+ <opcode> oso rexw rexb ; be ; rSIr14 Iv </opcode>
+ <opcode> oso rexw rexb ; bf ; rDIr15 Iv </opcode>
+ <opcode> rexr ; 0f 20 ; R C </opcode>
+ <opcode> rexr ; 0f 21 ; R D </opcode>
+ <opcode> rexr ; 0f 22 ; C R </opcode>
+ <opcode> rexr ; 0f 23 ; D R </opcode>
+ </instruction>
+
+ <instruction mnemonic="movapd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 28 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f 29 ; W V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movaps">
+ <opcode> aso rexr rexx rexb ; 0f 28 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 29 ; W V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movd">
+ <opcode cast="2"> aso rexw rexr rexx rexb ; sse66 0f 6e ; V Ex </opcode>
+ <opcode cast="2"> aso rexr rexx rexb ; 0f 6e ; P Ex </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; sse66 0f 7e ; Ex V </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; 0f 7e ; Ex P </opcode>
+ </instruction>
+
+ <instruction mnemonic="movddup">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 12 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="movdqa">
+ <opcode> aso rexr rexx rexb ; sse66 0f 7f ; W V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movdqu">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 6f ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; ssef3 0f 7f ; W V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movdq2q">
+ <opcode> aso rexb ; ssef2 0f d6 ; P VR </opcode>
+ </instruction>
+
+ <instruction mnemonic="movhpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 16 ; V M </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f 17 ; M V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movhps">
+ <opcode> aso rexr rexx rexb ; 0f 16 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 17 ; M V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movlhps"></instruction>
+
+ <instruction mnemonic="movlpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 12 ; V M </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f 13 ; M V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movlps">
+ <opcode> aso rexr rexx rexb ; 0f 12 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 13 ; M V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movhlps"></instruction>
+
+ <instruction mnemonic="movmskpd">
+ <opcode> oso rexr rexb ; sse66 0f 50 ; Gd VR </opcode>
+ </instruction>
+
+ <instruction mnemonic="movmskps">
+ <opcode> oso rexr rexb ; 0f 50 ; Gd VR </opcode>
+ </instruction>
+
+ <instruction mnemonic="movntdq">
+ <opcode> aso rexr rexx rexb ; sse66 0f e7 ; M V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movnti">
+ <opcode> aso rexw rexr rexx rexb ; 0f c3 ; M Gvw </opcode>
+ </instruction>
+
+ <instruction mnemonic="movntpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 2b ; M V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movntps">
+ <opcode> aso rexr rexx rexb ; 0f 2b ; M V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movntq">
+ <opcode> 0f e7 ; M P </opcode>
+ </instruction>
+
+ <instruction mnemonic="movq">
+ <opcode> aso rexr rexx rexb ; 0f 6f ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f d6 ; W V </opcode>
+ <opcode> aso rexr rexx rexb ; ssef3 0f 7e ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 7f ; Q P </opcode>
+ </instruction>
+
+ <instruction mnemonic="movqa">
+ <opcode> aso rexr rexx rexb ; sse66 0f 6f ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="movq2dq">
+ <opcode> aso ; ssef3 0f d6 ; V PR </opcode>
+ </instruction>
+
+ <instruction mnemonic="movsb">
+ <opcode imp_addr="1"> a4 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="movsw">
+ <opcode imp_addr="1"> oso rexw ; a5 /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="movsd">
+ <opcode imp_addr="1"> oso rexw ; a5 /O32 ; </opcode>
+ <opcode> aso rexr rexx rexb ; ssef2 0f 10 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; ssef2 0f 11 ; W V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movsq">
+ <opcode imp_addr="1"> oso rexw ; a5 /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="movsldup">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 12 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="movshdup">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 16 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="movss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 10 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; ssef3 0f 11 ; W V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movsx">
+ <opcode cast="2"> aso oso rexw rexr rexx rexb ; 0f be ; Gv Eb </opcode>
+ <opcode cast="2"> aso oso rexw rexr rexx rexb ; 0f bf ; Gv Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="movupd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 10 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f 11 ; W V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movups">
+ <opcode> aso rexr rexx rexb ; 0f 10 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 11 ; W V </opcode>
+ </instruction>
+
+ <instruction mnemonic="movzx">
+ <opcode cast="2"> aso oso rexw rexr rexx rexb ; 0f b6 ; Gv Eb </opcode>
+ <opcode cast="2"> aso oso rexw rexr rexx rexb ; 0f b7 ; Gv Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="mul">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; F6 /4 ; Eb </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; F7 /4 ; Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="mulpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 59 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="mulps">
+ <opcode> aso rexr rexx rexb ; 0f 59 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="mulsd">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 59 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="mulss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 59 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="mwait">
+ <opcode> 0F 01 /1 /mod=11 /rm=1 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="neg">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; F6 /3 ; Eb </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; F7 /3 ; Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="nop">
+ <opcode> ; 90 ; </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 19 ; M </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 1a ; M </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 1b ; M </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 1c ; M </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 1d ; M </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 1e ; M </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 1f ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="not">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; F6 /2 ; Eb </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; F7 /2 ; Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="or">
+ <opcode> aso rexr rexx rexb ; 08 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 09 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 0a ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 0b ; Gv Ev </opcode>
+ <opcode> ; 0c ; AL Ib </opcode>
+ <opcode> oso rexw ; 0d ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; 80 /1 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 81 /1 ; Ev Iz </opcode>
+ <opcode mode="inv64" cast="1"> aso rexr rexx rexb ; 82 /1 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 83 /1 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="orpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 56 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="orps">
+ <opcode> aso rexr rexx rexb ; 0f 56 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="out">
+ <opcode> ; e6 ; Ib AL </opcode>
+ <opcode> oso ; e7 ; Ib eAX </opcode>
+ <opcode> ; ee ; DX AL </opcode>
+ <opcode> oso ; ef ; DX eAX </opcode>
+ </instruction>
+
+ <instruction mnemonic="outsb">
+ <opcode> 6e ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="outsw">
+ <opcode> oso ; 6f /o16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="outsd">
+ <opcode> oso ; 6f /o32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="outsq">
+ <opcode> oso ; 6f /o64; </opcode>
+ </instruction>
+
+ <instruction mnemonic="packsswb">
+ <opcode> aso rexr rexx rexb ; sse66 0f 63 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 63 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="packssdw">
+ <opcode> aso rexr rexx rexb ; sse66 0f 6b ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 6b ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="packuswb">
+ <opcode> aso rexr rexx rexb ; sse66 0f 67 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 67 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="paddb">
+ <opcode> aso rexr rexx rexb ; sse66 0f fc ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f fc ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="paddw">
+ <opcode> aso rexr rexx rexb ; 0f fd ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f fd ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="paddq">
+ <opcode> aso rexr rexx rexb ; 0f d4 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f d4 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="paddsb">
+ <opcode> aso rexr rexx rexb ; 0f ec ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f ec ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="paddsw">
+ <opcode> aso rexr rexx rexb ; 0f ed ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f ed ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="paddusb">
+ <opcode> aso rexr rexx rexb ; 0f dc ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="paddusw">
+ <opcode> aso rexr rexx rexb ; 0f dd ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pand">
+ <opcode> aso rexr rexx rexb ; sse66 0f db ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f db ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pandn">
+ <opcode> aso rexr rexx rexb ; sse66 0f df ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f df ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pause">
+ <opcode> ; f3 90 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="pavgb">
+ <opcode> aso rexr rexx rexb ; sse66 0f e0 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f e0 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pavgw">
+ <opcode> aso rexr rexx rexb ; sse66 0f e3 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f e3 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pcmpeqb">
+ <opcode> aso rexr rexx rexb ; 0f 74 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f 74 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pcmpeqw">
+ <opcode> aso rexr rexx rexb ; 0f 75 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f 75 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pcmpeqd">
+ <opcode> aso rexr rexx rexb ; 0f 76 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f 76 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pcmpgtb">
+ <opcode> aso rexr rexx rexb ; sse66 0f 64 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 64 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pcmpgtw">
+ <opcode> aso rexr rexx rexb ; sse66 0f 65 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 65 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pcmpgtd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 66 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 66 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pextrw">
+ <opcode> aso rexr rexb ; sse66 0f c5 ; Gd VR Ib </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 0f c5 ; Gd PR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="pinsrw">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f c4 ; P Ew Ib </opcode>
+ <opcode> aso rexw rexr rexx rexb ; sse66 0f c4 ; V Ew Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmaddwd">
+ <opcode> aso rexr rexx rexb ; 0f f5 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f f5 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmaxsw">
+ <opcode> aso rexr rexx rexb ; sse66 0f ee ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f ee ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmaxub">
+ <opcode> aso rexr rexx rexb ; 0f de ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f de ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pminsw">
+ <opcode> aso rexr rexx rexb ; sse66 0f ea ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f ea ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pminub">
+ <opcode> aso rexr rexx rexb ; sse66 0f da ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f da ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmovmskb">
+ <opcode> rexr rexb ; sse66 0f d7 ; Gd VR </opcode>
+ <opcode> oso rexr rexb ; 0f d7 ; Gd PR </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmulhuw">
+ <opcode> aso rexr rexx rexb ; 0f e4 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f e4 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmulhw">
+ <opcode> aso rexr rexx rexb ; sse66 0f e5 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f e5 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmullw">
+ <opcode> aso rexr rexx rexb ; 0f d5 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f d5 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmuludq">
+ <opcode> aso rexr rexx rexb ; 0f f4 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f f4 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pop">
+ <opcode mode="inv64"> ; 07 ; ES </opcode>
+ <opcode mode="inv64"> ; 17 ; SS </opcode>
+ <opcode mode="inv64"> ; 1f ; DS </opcode>
+ <opcode> 0f a9 ; GS </opcode>
+ <opcode> 0f a1 ; FS </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 58 ; rAXr8 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 59 ; rCXr9 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 5A ; rDXr10 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 5B ; rBXr11 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 5C ; rSPr12 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 5D ; rBPr13 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 5E ; rSIr14 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 5F ; rDIr15 </opcode>
+ <opcode mode="def64 depM" cast="1"> aso oso rexw rexr rexx rexb ; 8F /0 ; Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="popa">
+ <opcode mode="inv64"> oso ; 61 /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="popad">
+ <opcode mode="inv64"> oso ; 61 /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="popfw">
+ <opcode mode="def64 depM"> oso ; 9d /M32 /O16 ; </opcode>
+ <opcode mode="def64 depM"> oso ; 9d /M16 /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="popfd">
+ <opcode mode="def64 depM"> oso ; 9d /M16 /O32 ; </opcode>
+ <opcode mode="def64 depM"> oso ; 9d /M32 /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="popfq">
+ <opcode mode="def64 depM"> oso ; 9d /M64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="por">
+ <opcode> aso rexr rexx rexb ; sse66 0f eb ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f eb ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="prefetch">
+ <opcode> aso rexw rexr rexx rexb ; 0F 0D /0 ; M </opcode>
+ <opcode> aso rexw rexr rexx rexb ; 0F 0D /1 ; M </opcode>
+ <opcode> aso rexw rexr rexx rexb ; 0F 0D /2 ; M </opcode>
+ <opcode> aso rexw rexr rexx rexb ; 0F 0D /3 ; M </opcode>
+ <opcode> aso rexw rexr rexx rexb ; 0F 0D /4 ; M </opcode>
+ <opcode> aso rexw rexr rexx rexb ; 0F 0D /5 ; M </opcode>
+ <opcode> aso rexw rexr rexx rexb ; 0F 0D /6 ; M </opcode>
+ <opcode> aso rexw rexr rexx rexb ; 0F 0D /7 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="prefetchnta">
+ <opcode> aso rexw rexr rexx rexb ; 0F 18 /0 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="prefetcht0">
+ <opcode> aso rexw rexr rexx rexb ; 0F 18 /1 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="prefetcht1">
+ <opcode> aso rexw rexr rexx rexb ; 0F 18 /2 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="prefetcht2">
+ <opcode> aso rexw rexr rexx rexb ; 0F 18 /3 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="psadbw">
+ <opcode> aso rexr rexx rexb ; sse66 0f f6 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f f6 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pshufd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 70 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="pshufhw">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 70 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="pshuflw">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 70 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="pshufw">
+ <opcode> aso rexr rexx rexb ; 0f 70 ; P Q Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="pslldq">
+ <opcode> rexb ; sse66 0F 73 /7 ; VR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psllw">
+ <opcode> aso rexr rexx rexb ; sse66 0f f1 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f f1 ; P Q </opcode>
+ <opcode> rexb ; sse66 0F 71 /6 ; VR Ib </opcode>
+ <opcode> 0F 71 /6 ; PR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="pslld">
+ <opcode> aso rexr rexx rexb ; sse66 0f f2 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f f2 ; P Q </opcode>
+ <opcode> rexb ; sse66 0F 72 /6 ; VR Ib </opcode>
+ <opcode> 0F 72 /6 ; PR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psllq">
+ <opcode> aso rexr rexx rexb ; sse66 0f f3 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f f3 ; P Q </opcode>
+ <opcode> rexb ; sse66 0F 73 /6 ; VR Ib </opcode>
+ <opcode> 0F 73 /6 ; PR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psraw">
+ <opcode> aso rexr rexx rexb ; 0f e1 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f e1 ; V W </opcode>
+ <opcode> rexb ; sse66 0F 71 /4 ; VR Ib </opcode>
+ <opcode> 0F 71 /4 ; PR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psrad">
+ <opcode> 0F 72 /4 ; PR Ib </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f e2 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f e2 ; P Q </opcode>
+ <opcode> rexb ; sse66 0F 72 /4 ; VR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psrlw">
+ <opcode> 0F 71 /2 ; PR Ib </opcode>
+ <opcode> aso rexr rexx rexb ; 0f d1 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f d1 ; V W </opcode>
+ <opcode> rexb ; sse66 0F 71 /2 ; VR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psrld">
+ <opcode> 0F 72 /2 ; PR Ib </opcode>
+ <opcode> aso rexr rexx rexb ; 0f d2 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f d2 ; V W </opcode>
+ <opcode> rexb ; sse66 0F 72 /2 ; VR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psrlq">
+ <opcode> 0F 73 /2 ; PR Ib </opcode>
+ <opcode> aso rexr rexx rexb ; 0f d3 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f d3 ; V W </opcode>
+ <opcode> rexb ; sse66 0F 73 /2 ; VR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psrldq">
+ <opcode> rexb ; sse66 0F 73 /3 ; VR Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="psubb">
+ <opcode> aso rexr rexx rexb ; sse66 0f f8 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f f8 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="psubw">
+ <opcode> aso rexr rexx rexb ; sse66 0f f9 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f f9 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="psubd">
+ <opcode> aso rexr rexx rexb ; 0f fa ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f fa ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="psubq">
+ <opcode> aso rexr rexx rexb ; sse66 0f fb ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f fb ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="psubsb">
+ <opcode> aso rexr rexx rexb ; 0f e8 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f e8 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="psubsw">
+ <opcode> aso rexr rexx rexb ; 0f e9 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f e9 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="psubusb">
+ <opcode> aso rexr rexx rexb ; 0f d8 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f d8 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f dc ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="psubusw">
+ <opcode> aso rexr rexx rexb ; 0f d9 ; P Q </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f d9 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="punpckhbw">
+ <opcode> aso rexr rexx rexb ; sse66 0f 68 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; sse66 0f dd ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 68 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="punpckhwd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 69 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 69 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="punpckhdq">
+ <opcode> aso rexr rexx rexb ; sse66 0f 6a ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 6a ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="punpckhqdq">
+ <opcode> aso rexr rexx rexb ; sse66 0f 6d ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="punpcklbw">
+ <opcode> aso rexr rexx rexb ; sse66 0f 60 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 60 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="punpcklwd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 61 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 61 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="punpckldq">
+ <opcode> aso rexr rexx rexb ; sse66 0f 62 ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f 62 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="punpcklqdq">
+ <opcode> aso rexr rexx rexb ; sse66 0f 6c ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="pi2fw">
+ <opcode> ; 0f 0f /3dnow=0C ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pi2fd">
+ <opcode> ; 0f 0f /3dnow=0D ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pf2iw">
+ <opcode> ; 0f 0f /3dnow=1C ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pf2id">
+ <opcode> ; 0f 0f /3dnow=1D ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfnacc">
+ <opcode> ; 0f 0f /3dnow=8A ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfpnacc">
+ <opcode> ; 0f 0f /3dnow=8E ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfcmpge">
+ <opcode> ; 0f 0f /3dnow=90 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfmin">
+ <opcode> ; 0f 0f /3dnow=94 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfrcp">
+ <opcode> ; 0f 0f /3dnow=96 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfrsqrt">
+ <opcode> ; 0f 0f /3dnow=97 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfsub">
+ <opcode> ; 0f 0f /3dnow=9A ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfadd">
+ <opcode> ; 0f 0f /3dnow=9E ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfcmpgt">
+ <opcode> ; 0f 0f /3dnow=A0 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfmax">
+ <opcode> ; 0f 0f /3dnow=A4 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfrcpit1">
+ <opcode> ; 0f 0f /3dnow=A6 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfrspit1">
+ <opcode> ; 0f 0f /3dnow=A7 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfsubr">
+ <opcode> ; 0f 0f /3dnow=AA ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfacc">
+ <opcode> ; 0f 0f /3dnow=AE ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfcmpeq">
+ <opcode> ; 0f 0f /3dnow=B0 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfmul">
+ <opcode> ; 0f 0f /3dnow=B4 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pfrcpit2">
+ <opcode> ; 0f 0f /3dnow=B6 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pmulhrw">
+ <opcode> ; 0f 0f /3dnow=B7 ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pswapd">
+ <opcode> ; 0f 0f /3dnow=BB ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="pavgusb">
+ <opcode> ; 0f 0f /3dnow=BF ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="push">
+ <opcode mode="inv64"> ; 06 ; ES </opcode>
+ <opcode mode="inv64"> ; 0e ; CS </opcode>
+ <opcode mode="inv64"> ; 16 ; SS </opcode>
+ <opcode mode="inv64"> ; 1e ; DS </opcode>
+ <opcode> ; 0f a8 ; GS </opcode>
+ <opcode> ; 0f a0 ; FS </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 50 ; rAXr8 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 51 ; rCXr9 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 52 ; rDXr10 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 53 ; rBXr11 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 54 ; rSPr12 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 55 ; rBPr13 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 56 ; rSIr14 </opcode>
+ <opcode mode="def64 depM"> oso rexb ; 57 ; rDIr15 </opcode>
+ <opcode cast="1"> oso ; 68 ; Iz </opcode>
+ <opcode mode="def64" cast="1"> aso oso rexw rexr rexx rexb ; FF /6 ; Ev </opcode>
+ <opcode> ; 6a ; Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="pusha">
+ <opcode mode="inv64"> oso ; 60 /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="pushad">
+ <opcode mode="inv64"> oso ; 60 /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="pushfw">
+ <opcode mode="def64"> oso ; 9c /M32 /O16 ; </opcode>
+ <opcode mode="def64"> oso ; 9c /M16 /O16 ; </opcode>
+ <opcode mode="def64"> oso rexw ; 9c /M64 /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="pushfd">
+ <opcode mode="def64"> oso ; 9c /M16 /O32 ; </opcode>
+ <opcode mode="def64"> oso ; 9c /M32 /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="pushfq">
+ <opcode mode="def64"> oso rexw ; 9c /M64 /O32 ; </opcode>
+ <opcode mode="def64"> oso rexw ; 9c /M64 /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="pxor">
+ <opcode> aso rexr rexx rexb ; sse66 0f ef ; V W </opcode>
+ <opcode> aso rexr rexx rexb ; 0f ef ; P Q </opcode>
+ </instruction>
+
+ <instruction mnemonic="rcl">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C0 /2 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C1 /2 ; Ev Ib </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D0 /2 ; Eb I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D2 /2 ; Eb CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D3 /2 ; Ev CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D1 /2 ; Ev I1 </opcode>
+ </instruction>
+
+ <instruction mnemonic="rcr">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D0 /3 ; Eb I1 </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C1 /3 ; Ev Ib </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C0 /3 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D1 /3 ; Ev I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D2 /3 ; Eb CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D3 /3 ; Ev CL </opcode>
+ </instruction>
+
+ <instruction mnemonic="rol">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C0 /0 ; Eb Ib </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D0 /0 ; Eb I1 </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D1 /0 ; Ev I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D2 /0 ; Eb CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D3 /0 ; Ev CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C1 /0 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="ror">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D0 /1 ; Eb I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C0 /1 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C1 /1 ; Ev Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D1 /1 ; Ev I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D2 /1 ; Eb CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D3 /1 ; Ev CL </opcode>
+ </instruction>
+
+ <instruction mnemonic="rcpps">
+ <opcode> aso rexr rexx rexb ; 0f 53 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="rcpss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 53 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="rdmsr">
+ <opcode> 0f 32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="rdpmc">
+ <opcode> 0f 33 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="rdtsc">
+ <opcode> 0f 31 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="rdtscp">
+ <opcode> 0F 01 /7 /mod=11 /rm=1 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="repne">
+ <opcode> f2 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="rep">
+ <opcode> f3 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="ret">
+ <opcode> ; c2 ; Iw </opcode>
+ <opcode> ; c3 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="retf">
+ <opcode> ; ca ; Iw </opcode>
+ <opcode> ; cb ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="rsm">
+ <opcode> 0f aa ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="rsqrtps">
+ <opcode> aso rexr rexx rexb ; 0f 52 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="rsqrtss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 52 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="sahf">
+ <opcode> ; 9e ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="sal">
+
+ </instruction>
+
+ <instruction mnemonic="salc">
+ <opcode mode="inv64"> ; d6 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="sar">
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D1 /7 ; Ev I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C0 /7 ; Eb Ib </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D0 /7 ; Eb I1 </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C1 /7 ; Ev Ib </opcode>
+ <opcode> aso rexw rexr rexx rexb ; D2 /7 ; Eb CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D3 /7 ; Ev CL </opcode>
+ </instruction>
+
+ <instruction mnemonic="shl">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C0 /6 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C1 /6 ; Ev Ib </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D0 /6 ; Eb I1 </opcode>
+ <opcode> aso rexw rexr rexx rexb ; D2 /6 ; Eb CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D3 /6 ; Ev CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C1 /4 ; Ev Ib </opcode>
+ <opcode> aso rexr rexx rexb ; D2 /4 ; Eb CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D1 /4 ; Ev I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D0 /4 ; Eb I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C0 /4 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D3 /4 ; Ev CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D1 /6 ; Ev I1 </opcode>
+ </instruction>
+
+ <instruction mnemonic="shr">
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; C1 /5 ; Ev Ib </opcode>
+ <opcode> aso rexw rexr rexx rexb ; D2 /5 ; Eb CL </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D1 /5 ; Ev I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; D0 /5 ; Eb I1 </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; C0 /5 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; D3 /5 ; Ev CL </opcode>
+ </instruction>
+
+ <instruction mnemonic="sbb">
+ <opcode> aso rexr rexx rexb ; 18 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 19 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 1a ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 1b ; Gv Ev </opcode>
+ <opcode> ; 1c ; AL Ib </opcode>
+ <opcode> oso rexw ; 1d ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; 80 /3 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 81 /3 ; Ev Iz </opcode>
+ <opcode mode="inv64" cast="1"> aso rexr rexx rexb ; 82 /3 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 83 /3 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="scasb">
+ <opcode> ; ae ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="scasw">
+ <opcode> oso rexw ; af /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="scasd">
+ <opcode> oso rexw ; af /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="scasq">
+ <opcode> oso rexw ; af /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="seto">
+ <opcode> aso rexr rexx rexb ; 0f 90 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setno">
+ <opcode> aso rexr rexx rexb ; 0f 91 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setb">
+ <opcode> aso rexr rexx rexb ; 0f 92 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setnb">
+ <opcode> aso rexr rexx rexb ; 0f 93 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setz">
+ <opcode> aso rexr rexx rexb ; 0f 94 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setnz">
+ <opcode> aso rexr rexx rexb ; 0f 95 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setbe">
+ <opcode> aso rexr rexx rexb ; 0f 96 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="seta">
+ <opcode> aso rexr rexx rexb ; 0f 97 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="sets">
+ <opcode> aso rexr rexx rexb ; 0f 98 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setns">
+ <opcode> aso rexr rexx rexb ; 0f 99 ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setp">
+ <opcode> aso rexr rexx rexb ; 0f 9a ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setnp">
+ <opcode> aso rexr rexx rexb ; 0f 9b ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setl">
+ <opcode> aso rexr rexx rexb ; 0f 9c ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setge">
+ <opcode> aso rexr rexx rexb ; 0f 9d ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setle">
+ <opcode> aso rexr rexx rexb ; 0f 9e ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="setg">
+ <opcode> aso rexr rexx rexb ; 0f 9f ; Eb </opcode>
+ </instruction>
+
+ <instruction mnemonic="sfence">
+ <opcode> 0F AE /7 /mod=11 /rm=0 ; </opcode>
+ <opcode> 0F AE /7 /mod=11 /rm=1 ; </opcode>
+ <opcode> 0F AE /7 /mod=11 /rm=2 ; </opcode>
+ <opcode> 0F AE /7 /mod=11 /rm=3 ; </opcode>
+ <opcode> 0F AE /7 /mod=11 /rm=4 ; </opcode>
+ <opcode> 0F AE /7 /mod=11 /rm=5 ; </opcode>
+ <opcode> 0F AE /7 /mod=11 /rm=6 ; </opcode>
+ <opcode> 0F AE /7 /mod=11 /rm=7 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="sgdt">
+ <opcode> aso rexr rexx rexb ; 0F 01 /0 /mod=!11 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="shld">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f a4 ; Ev Gv Ib </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 0f a5 ; Ev Gv CL </opcode>
+ </instruction>
+
+ <instruction mnemonic="shrd">
+ <opcode> aso oso rexw rexr rexx rexb ; 0f ac ; Ev Gv Ib </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 0f ad ; Ev Gv CL </opcode>
+ </instruction>
+
+ <instruction mnemonic="shufpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f c6 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="shufps">
+ <opcode> aso rexr rexx rexb ; 0f c6 ; V W Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="sidt">
+ <opcode> aso rexr rexx rexb ; 0F 01 /1 /mod=!11 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="sldt">
+ <opcode> aso oso rexr rexx rexb ; 0F 00 /0 ; Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="smsw">
+ <opcode> aso rexr rexx rexb ; 0F 01 /4 /mod=!11 ; M </opcode>
+ </instruction>
+
+ <instruction mnemonic="sqrtps">
+ <opcode> aso rexr rexx rexb ; 0f 51 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="sqrtpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 51 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="sqrtsd">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 51 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="sqrtss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 51 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="stc">
+ <opcode> f9 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="std">
+ <opcode> fd ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="stgi">
+ <opcode> 0F 01 /3 /mod=11 /rm=4 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="sti">
+ <opcode> fb ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="skinit">
+ <opcode> 0F 01 /3 /mod=11 /rm=6 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="stmxcsr">
+ <opcode> aso rexw rexr rexx rexb ; 0F AE /3 ; Md </opcode>
+ </instruction>
+
+ <instruction mnemonic="stosb">
+ <opcode imp_addr="1"> ; aa ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="stosw">
+ <opcode imp_addr="1"> oso rexw ; ab /O16 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="stosd">
+ <opcode imp_addr="1"> oso rexw ; ab /O32 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="stosq">
+ <opcode imp_addr="1"> oso rexw ; ab /O64 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="str">
+ <opcode> aso oso rexr rexx rexb ; 0F 00 /1 ; Ev </opcode>
+ </instruction>
+
+ <instruction mnemonic="sub">
+ <opcode> aso rexr rexx rexb ; 28 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 29 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 2a ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 2b ; Gv Ev </opcode>
+ <opcode> 2c ; AL Ib </opcode>
+ <opcode> oso rexw ; 2d ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; 80 /5 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 81 /5 ; Ev Iz </opcode>
+ <opcode mode="inv64" cast="1"> aso rexr rexx rexb ; 82 /5 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 83 /5 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="subpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 5c ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="subps">
+ <opcode> aso rexr rexx rexb ; 0f 5c ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="subsd">
+ <opcode> aso rexr rexx rexb ; ssef2 0f 5c ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="subss">
+ <opcode> aso rexr rexx rexb ; ssef3 0f 5c ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="swapgs">
+ <opcode> 0F 01 /7 /mod=11 /rm=0 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="syscall">
+ <opcode> 0f 05 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="sysenter">
+ <opcode mode="inv64"> 0f 34 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="sysexit">
+ <opcode> 0f 35 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="sysret">
+ <opcode> 0f 07 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="test">
+ <opcode cast="1"> aso rexw rexr rexx rexb ; F6 /0 ; Eb Ib </opcode>
+ <opcode> aso rexr rexx rexb ; 84 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 85 ; Ev Gv </opcode>
+ <opcode> a8 ; AL Ib </opcode>
+ <opcode> oso rexw ; a9 ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexw rexr rexx rexb ; F6 /1 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; F7 /0 ; Ev Iz </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; F7 /1 ; Ev Iz </opcode>
+ </instruction>
+
+
+ <instruction mnemonic="ucomisd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 2e ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="ucomiss">
+ <opcode> aso rexr rexx rexb ; 0f 2e ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="ud2">
+ <opcode> 0f 0b ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="unpckhpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 15 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="unpckhps">
+ <opcode> aso rexr rexx rexb ; 0f 15 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="unpcklps">
+ <opcode> aso rexr rexx rexb ; 0f 14 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="unpcklpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 14 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="verr">
+ <opcode> aso rexr rexx rexb ; 0F 00 /4 ; Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="verw">
+ <opcode> aso rexr rexx rexb ; 0F 00 /5 ; Ew </opcode>
+ </instruction>
+
+ <instruction mnemonic="vmcall">
+ <opcode> 0F 01 /0 /mod=11 /rm=1 ; </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmclear">
+ <opcode> aso rexr rexx rexb ; sse66 0F C7 /6 ; Mq </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmxon">
+ <opcode> aso rexr rexx rexb ; ssef3 0F C7 /6 ; Mq </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmptrld">
+ <opcode> aso rexr rexx rexb ; 0F C7 /6 ; Mq </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmptrst">
+ <opcode> aso rexr rexx rexb ; 0F C7 /7 ; Mq </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmlaunch">
+ <opcode> 0F 01 /0 /mod=11 /rm=2 ; </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmresume">
+ <opcode> 0F 01 /0 /mod=11 /rm=3 ; </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmxoff">
+ <opcode> 0F 01 /0 /mod=11 /rm=4 ; </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmread">
+ <opcode mode="def64"> aso rexr rexx rexb ; 0F 78 /M16 ; Ed Gd </opcode>
+ <opcode mode="def64"> aso rexr rexx rexb ; 0F 78 /M32 ; Ed Gd </opcode>
+ <opcode mode="def64"> aso rexr rexx rexb ; 0F 78 /M64 ; Eq Gq </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmwrite">
+ <opcode mode="def64"> aso rexr rexx rexb ; 0F 79 /M16 ; Gd Ed </opcode>
+ <opcode mode="def64"> aso rexr rexx rexb ; 0F 79 /M32 ; Gd Ed </opcode>
+ <opcode mode="def64"> aso rexr rexx rexb ; 0F 79 /M64 ; Gq Eq </opcode>
+ <vendor> INTEL </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmrun">
+ <opcode> 0F 01 /3 /mod=11 /rm=0 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmmcall">
+ <opcode> 0F 01 /3 /mod=11 /rm=1 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmload">
+ <opcode> 0F 01 /3 /mod=11 /rm=2 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="vmsave">
+ <opcode> 0F 01 /3 /mod=11 /rm=3 ; </opcode>
+ <vendor> AMD </vendor>
+ </instruction>
+
+ <instruction mnemonic="wait">
+ <opcode> ; 9b ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="wbinvd">
+ <opcode> 0f 09 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="wrmsr">
+ <opcode> 0f 30 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xadd">
+ <opcode> aso oso rexr rexx rexb ; 0f c0 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; sse66 0f c1 ; Ev Gv </opcode>
+ <opcode> aso rexw rexr rexx rexb ; sse66 0f c0 ; Eb Gb </opcode>
+ <opcode> aso rexw rexr rexx rexb ; ssef2 0f c0 ; Eb Gb </opcode>
+ <opcode> aso oso rexr rexx rexb ; ssef2 0f c1 ; Ev Gv </opcode>
+ <opcode> aso rexw rexr rexx rexb ; ssef3 0f c0 ; Eb Gb </opcode>
+ <opcode> aso rexw rexr rexx rexb ; ssef3 0f c1 ; Ev Gv </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 0f c1 ; Ev Gv </opcode>
+ </instruction>
+
+ <instruction mnemonic="xchg">
+ <opcode> aso rexr rexx rexb ; 86 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 87 ; Ev Gv </opcode>
+ <opcode> oso rexw rexb ; 90 ; rAXr8 rAX </opcode>
+ <opcode> oso rexw rexb ; 91 ; rCXr9 rAX </opcode>
+ <opcode> oso rexw rexb ; 92 ; rDXr10 rAX </opcode>
+ <opcode> oso rexw rexb ; 93 ; rBXr11 rAX </opcode>
+ <opcode> oso rexw rexb ; 94 ; rSPr12 rAX </opcode>
+ <opcode> oso rexw rexb ; 95 ; rBPr13 rAX </opcode>
+ <opcode> oso rexw rexb ; 96 ; rSIr14 rAX </opcode>
+ <opcode> oso rexw rexb ; 97 ; rDIr15 rAX </opcode>
+ </instruction>
+
+ <instruction mnemonic="xlatb">
+ <opcode> rexw ; d7 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xor">
+ <opcode> aso rexr rexx rexb ; 30 ; Eb Gb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 31 ; Ev Gv </opcode>
+ <opcode> aso rexr rexx rexb ; 32 ; Gb Eb </opcode>
+ <opcode> aso oso rexw rexr rexx rexb ; 33 ; Gv Ev </opcode>
+ <opcode> ; 34 ; AL Ib </opcode>
+ <opcode> oso rexw ; 35 ; rAX Iz </opcode>
+ <opcode cast="1"> aso rexr rexx rexb ; 80 /6 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 81 /6 ; Ev Iz </opcode>
+ <opcode mode="inv64" cast="1"> aso rexr rexx rexb ; 82 /6 ; Eb Ib </opcode>
+ <opcode cast="1"> aso oso rexw rexr rexx rexb ; 83 /6 ; Ev Ib </opcode>
+ </instruction>
+
+ <instruction mnemonic="xorpd">
+ <opcode> aso rexr rexx rexb ; sse66 0f 57 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="xorps">
+ <opcode> aso rexr rexx rexb ; 0f 57 ; V W </opcode>
+ </instruction>
+
+ <instruction mnemonic="xcryptecb">
+ <opcode> ; 0f a7 /mod=11 /rm=0 /1 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xcryptcbc">
+ <opcode> ; 0f a7 /mod=11 /rm=0 /2 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xcryptctr">
+ <opcode> ; 0f a7 /mod=11 /rm=0 /3 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xcryptcfb">
+ <opcode> ; 0f a7 /mod=11 /rm=0 /4 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xcryptofb">
+ <opcode> ; 0f a7 /mod=11 /rm=0 /5 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xsha1">
+ <opcode> ; 0f a6 /mod=11 /rm=0 /1 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xsha256">
+ <opcode> ; 0f a6 /mod=11 /rm=0 /2 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="xstore">
+ <opcode> ; 0f a7 /mod=11 /rm=0 /0 ; </opcode>
+ </instruction>
+
+ <instruction mnemonic="db"></instruction>
+
+ <instruction mnemonic="invalid"></instruction>
+
+</x86optable>
--- /dev/null
+<xsl:stylesheet xmlns:xsl="http://www.w3.org/1999/XSL/Transform" version="1.0" >
+<xsl:template match="x86optable">
+<html>
+ <head>
+ <title>x86 opcode table</title>
+ <style>
+ .mnm {
+ border-bottom: 1px dotted #cdcdcd;
+ font-family: "lucida sans", georgia, helvetica, arial, verdana, georgia;
+ border-right: 1px solid #cdcdcd;
+ font-size: 1em;
+ }
+
+ .opc {
+ border-bottom: 1px dotted #cdcdcd;
+ border-right: 1px solid #cdcdcd;
+ font-family: monospace;
+ font-size: 1.1em;
+ }
+
+ .vdr {
+ border-bottom: 1px dotted #cdcdcd;
+ border-right: 1px solid #cdcdcd;
+ font-size: .9em;
+ }
+ </style>
+ </head>
+ <body>
+ <h1 style="text-align:left; padding-left:8px;">x86optable.xml</h1>
+ <p style="text-align:left; padding-left:8px">
+ <a style="text-decoration:none" href="http://udis86.sourceforge.net/">udis86.sourceforge.net</a></p>
+ <table cellpadding="4" cellspacing="6" width="800px">
+ <tr bgcolor='lightblue'>
+ <td align="center">Mnemonic</td>
+ <td align="center">Opcodes</td>
+ <td align="center">Vendor</td>
+ </tr>
+ <xsl:for-each select="instruction">
+ <tr>
+ <td class="mnm" align="center" valign="middle"><xsl:value-of select="@mnemonic"/></td>
+ <td class="opc">
+ <xsl:for-each select="opcode">
+ <xsl:apply-templates/>
+ <br/>
+ </xsl:for-each>
+ </td>
+ <td class="vdr" align="center" valign="top">
+ <xsl:for-each select="vendor">
+ <xsl:apply-templates/>
+ <br/>
+ </xsl:for-each>
+ </td>
+ </tr>
+ </xsl:for-each>
+ </table>
+ <p style="text-align:left; padding-left:8px">
+ <small>Copyright (c) 2008, Vivek Thampi</small>
+ </p>
+
+ </body>
+</html>
+</xsl:template>
+</xsl:stylesheet>
--- /dev/null
+lib_LTLIBRARIES = libudis86.la
+
+include_ladir = ${includedir}
+libudis86_ladir = ${includedir}/libudis86
+
+libudis86_la_SOURCES = itab.c \
+ input.c \
+ decode.c \
+ syn.c \
+ syn-intel.c \
+ syn-att.c \
+ udis86.c \
+ input.h \
+ syn.h \
+ decode.h \
+ extern.h \
+ types.h \
+ itab.h \
+ opgen.py
+
+libudis86_la_HEADERS = types.h extern.h itab.h
+
+# DLLs may not contain undefined symbol references. We have the linker
+# check this explicitly.
+if TARGET_WINDOWS
+libudis86_la_LDFLAGS=-no-undefined -version-info 0:0:0
+endif
+
+itab.c itab.h: ../docs/x86optable.xml opgen.py
+ python ./opgen.py $<
+
+clean-local:
+ rm -rf itab.c itab.h
--- /dev/null
+#
+# Makefile for win32 compilers
+#
+# (I need some help here.)
+#
+
+CC = cl
+CFLAGS = /O2
+AR = lib
+RM = del
+PERL = perl
+
+.SUFFIXES: .c .obj
+.c.obj:
+ $(CC) -c $(CFLAGS) -o $@ $<
+
+OBJS = itab.obj \
+ input.obj \
+ decode.obj \
+ input.obj \
+ decode.obj \
+ syn.obj \
+ syn-intel.obj \
+ syn-att.obj \
+ udis86.obj
+
+HDRS = types.h \
+ extern.h \
+ itab.h \
+ decode.h \
+ syn.h \
+ input.h
+
+libudis86.a: $(OBJS)
+ $(AR) /out:udis86.lib $(OBJS)
+
+itab.c itab.h: x86optable.xml opgen.py
+ python ./opgen.py
+
+itab.c input.c decode.c syn-intel.c syn-att.c syn.c udis86.c: $(HDRS)
+
+clean:
+ $(RM) *.obj *.lib
--- /dev/null
+/* udis86 - libudis86/decode.c
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __UD_STANDALONE__
+# include <string.h>
+#endif /* __UD_STANDALONE__ */
+
+#include "types.h"
+#include "itab.h"
+#include "input.h"
+#include "decode.h"
+
+/* The max number of prefixes to an instruction */
+#define MAX_PREFIXES 15
+
+static struct ud_itab_entry ie_invalid = { UD_Iinvalid, O_NONE, O_NONE, O_NONE, P_none };
+static struct ud_itab_entry ie_pause = { UD_Ipause, O_NONE, O_NONE, O_NONE, P_none };
+static struct ud_itab_entry ie_nop = { UD_Inop, O_NONE, O_NONE, O_NONE, P_none };
+
+
+/* Looks up mnemonic code in the mnemonic string table
+ * Returns NULL if the mnemonic code is invalid
+ */
+const char * ud_lookup_mnemonic( enum ud_mnemonic_code c )
+{
+ if ( c < UD_Id3vil )
+ return ud_mnemonics_str[ c ];
+ return NULL;
+}
+
+
+/* Extracts instruction prefixes.
+ */
+static int get_prefixes( struct ud* u )
+{
+ unsigned int have_pfx = 1;
+ unsigned int i;
+ uint8_t curr;
+
+ /* if in error state, bail out */
+ if ( u->error )
+ return -1;
+
+ /* keep going as long as there are prefixes available */
+ for ( i = 0; have_pfx ; ++i ) {
+
+ /* Get next byte. */
+ inp_next(u);
+ if ( u->error )
+ return -1;
+ curr = inp_curr( u );
+
+ /* rex prefixes in 64bit mode */
+ if ( u->dis_mode == 64 && ( curr & 0xF0 ) == 0x40 ) {
+ u->pfx_rex = curr;
+ } else {
+ switch ( curr )
+ {
+ case 0x2E :
+ u->pfx_seg = UD_R_CS;
+ u->pfx_rex = 0;
+ break;
+ case 0x36 :
+ u->pfx_seg = UD_R_SS;
+ u->pfx_rex = 0;
+ break;
+ case 0x3E :
+ u->pfx_seg = UD_R_DS;
+ u->pfx_rex = 0;
+ break;
+ case 0x26 :
+ u->pfx_seg = UD_R_ES;
+ u->pfx_rex = 0;
+ break;
+ case 0x64 :
+ u->pfx_seg = UD_R_FS;
+ u->pfx_rex = 0;
+ break;
+ case 0x65 :
+ u->pfx_seg = UD_R_GS;
+ u->pfx_rex = 0;
+ break;
+ case 0x67 : /* adress-size override prefix */
+ u->pfx_adr = 0x67;
+ u->pfx_rex = 0;
+ break;
+ case 0xF0 :
+ u->pfx_lock = 0xF0;
+ u->pfx_rex = 0;
+ break;
+ case 0x66:
+ /* the 0x66 sse prefix is only effective if no other sse prefix
+ * has already been specified.
+ */
+ if ( !u->pfx_insn ) u->pfx_insn = 0x66;
+ u->pfx_opr = 0x66;
+ u->pfx_rex = 0;
+ break;
+ case 0xF2:
+ u->pfx_insn = 0xF2;
+ u->pfx_repne = 0xF2;
+ u->pfx_rex = 0;
+ break;
+ case 0xF3:
+ u->pfx_insn = 0xF3;
+ u->pfx_rep = 0xF3;
+ u->pfx_repe = 0xF3;
+ u->pfx_rex = 0;
+ break;
+ default :
+ /* No more prefixes */
+ have_pfx = 0;
+ break;
+ }
+ }
+
+ /* check if we reached max instruction length */
+ if ( i + 1 == MAX_INSN_LENGTH ) {
+ u->error = 1;
+ break;
+ }
+ }
+
+ /* return status */
+ if ( u->error )
+ return -1;
+
+ /* rewind back one byte in stream, since the above loop
+ * stops with a non-prefix byte.
+ */
+ inp_back(u);
+
+ /* speculatively determine the effective operand mode,
+ * based on the prefixes and the current disassembly
+ * mode. This may be inaccurate, but useful for mode
+ * dependent decoding.
+ */
+ if ( u->dis_mode == 64 ) {
+ u->opr_mode = REX_W( u->pfx_rex ) ? 64 : ( ( u->pfx_opr ) ? 16 : 32 ) ;
+ u->adr_mode = ( u->pfx_adr ) ? 32 : 64;
+ } else if ( u->dis_mode == 32 ) {
+ u->opr_mode = ( u->pfx_opr ) ? 16 : 32;
+ u->adr_mode = ( u->pfx_adr ) ? 16 : 32;
+ } else if ( u->dis_mode == 16 ) {
+ u->opr_mode = ( u->pfx_opr ) ? 32 : 16;
+ u->adr_mode = ( u->pfx_adr ) ? 32 : 16;
+ }
+
+ return 0;
+}
+
+
+/* Searches the instruction tables for the right entry.
+ */
+static int search_itab( struct ud * u )
+{
+ struct ud_itab_entry * e = NULL;
+ enum ud_itab_index table;
+ uint8_t peek;
+ uint8_t did_peek = 0;
+ uint8_t curr;
+ uint8_t index;
+
+ /* if in state of error, return */
+ if ( u->error )
+ return -1;
+
+ /* get first byte of opcode. */
+ inp_next(u);
+ if ( u->error )
+ return -1;
+ curr = inp_curr(u);
+
+ /* resolve xchg, nop, pause crazyness */
+ if ( 0x90 == curr ) {
+ if ( !( u->dis_mode == 64 && REX_B( u->pfx_rex ) ) ) {
+ if ( u->pfx_rep ) {
+ u->pfx_rep = 0;
+ e = & ie_pause;
+ } else {
+ e = & ie_nop;
+ }
+ goto found_entry;
+ }
+ }
+
+ /* get top-level table */
+ if ( 0x0F == curr ) {
+ table = ITAB__0F;
+ curr = inp_next(u);
+ if ( u->error )
+ return -1;
+
+ /* 2byte opcodes can be modified by 0x66, F3, and F2 prefixes */
+ if ( 0x66 == u->pfx_insn ) {
+ if ( ud_itab_list[ ITAB__PFX_SSE66__0F ][ curr ].mnemonic != UD_Iinvalid ) {
+ table = ITAB__PFX_SSE66__0F;
+ u->pfx_opr = 0;
+ }
+ } else if ( 0xF2 == u->pfx_insn ) {
+ if ( ud_itab_list[ ITAB__PFX_SSEF2__0F ][ curr ].mnemonic != UD_Iinvalid ) {
+ table = ITAB__PFX_SSEF2__0F;
+ u->pfx_repne = 0;
+ }
+ } else if ( 0xF3 == u->pfx_insn ) {
+ if ( ud_itab_list[ ITAB__PFX_SSEF3__0F ][ curr ].mnemonic != UD_Iinvalid ) {
+ table = ITAB__PFX_SSEF3__0F;
+ u->pfx_repe = 0;
+ u->pfx_rep = 0;
+ }
+ }
+ /* pick an instruction from the 1byte table */
+ } else {
+ table = ITAB__1BYTE;
+ }
+
+ index = curr;
+
+search:
+
+ e = & ud_itab_list[ table ][ index ];
+
+ /* if mnemonic constant is a standard instruction constant
+ * our search is over.
+ */
+
+ if ( e->mnemonic < UD_Id3vil ) {
+ if ( e->mnemonic == UD_Iinvalid ) {
+ if ( did_peek ) {
+ inp_next( u ); if ( u->error ) return -1;
+ }
+ goto found_entry;
+ }
+ goto found_entry;
+ }
+
+ table = e->prefix;
+
+ switch ( e->mnemonic )
+ {
+ case UD_Igrp_reg:
+ peek = inp_peek( u );
+ did_peek = 1;
+ index = MODRM_REG( peek );
+ break;
+
+ case UD_Igrp_mod:
+ peek = inp_peek( u );
+ did_peek = 1;
+ index = MODRM_MOD( peek );
+ if ( index == 3 )
+ index = ITAB__MOD_INDX__11;
+ else
+ index = ITAB__MOD_INDX__NOT_11;
+ break;
+
+ case UD_Igrp_rm:
+ curr = inp_next( u );
+ did_peek = 0;
+ if ( u->error )
+ return -1;
+ index = MODRM_RM( curr );
+ break;
+
+ case UD_Igrp_x87:
+ curr = inp_next( u );
+ did_peek = 0;
+ if ( u->error )
+ return -1;
+ index = curr - 0xC0;
+ break;
+
+ case UD_Igrp_3byte:
+ curr = inp_next( u );
+ did_peek = 0;
+ if (u->error)
+ return -1;
+ index = curr;
+ break;
+
+ case UD_Igrp_osize:
+ if ( u->opr_mode == 64 )
+ index = ITAB__MODE_INDX__64;
+ else if ( u->opr_mode == 32 )
+ index = ITAB__MODE_INDX__32;
+ else
+ index = ITAB__MODE_INDX__16;
+ break;
+
+ case UD_Igrp_asize:
+ if ( u->adr_mode == 64 )
+ index = ITAB__MODE_INDX__64;
+ else if ( u->adr_mode == 32 )
+ index = ITAB__MODE_INDX__32;
+ else
+ index = ITAB__MODE_INDX__16;
+ break;
+
+ case UD_Igrp_mode:
+ if ( u->dis_mode == 64 )
+ index = ITAB__MODE_INDX__64;
+ else if ( u->dis_mode == 32 )
+ index = ITAB__MODE_INDX__32;
+ else
+ index = ITAB__MODE_INDX__16;
+ break;
+
+ case UD_Igrp_vendor:
+ if ( u->vendor == UD_VENDOR_INTEL )
+ index = ITAB__VENDOR_INDX__INTEL;
+ else if ( u->vendor == UD_VENDOR_AMD )
+ index = ITAB__VENDOR_INDX__AMD;
+ else if ( u->vendor == UD_VENDOR_ANY )
+ index = ITAB__VENDOR_INDX__ANY;
+ else
+ return -1;
+ break;
+
+ case UD_Id3vil:
+ return -1;
+ break;
+
+ default:
+ return -1;
+ break;
+ }
+
+ goto search;
+
+found_entry:
+
+ u->itab_entry = e;
+ u->mnemonic = u->itab_entry->mnemonic;
+
+ return 0;
+}
+
+
+static unsigned int resolve_operand_size( const struct ud * u, unsigned int s )
+{
+ switch ( s )
+ {
+ case SZ_V:
+ return ( u->opr_mode );
+ case SZ_Z:
+ return ( u->opr_mode == 16 ) ? 16 : 32;
+ case SZ_P:
+ return ( u->opr_mode == 16 ) ? SZ_WP : SZ_DP;
+ case SZ_MDQ:
+ return ( u->opr_mode == 16 ) ? 32 : u->opr_mode;
+ case SZ_RDQ:
+ return ( u->dis_mode == 64 ) ? 64 : 32;
+ default:
+ return s;
+ }
+}
+
+
+static int resolve_mnemonic( struct ud* u )
+{
+ /* far/near flags */
+ u->br_far = 0;
+ u->br_near = 0;
+ /* readjust operand sizes for call/jmp instrcutions */
+ if ( u->mnemonic == UD_Icall || u->mnemonic == UD_Ijmp ) {
+ /* WP: 16bit pointer */
+ if ( u->operand[ 0 ].size == SZ_WP ) {
+ u->operand[ 0 ].size = 16;
+ u->br_far = 1;
+ u->br_near= 0;
+ /* DP: 32bit pointer */
+ } else if ( u->operand[ 0 ].size == SZ_DP ) {
+ u->operand[ 0 ].size = 32;
+ u->br_far = 1;
+ u->br_near= 0;
+ } else {
+ u->br_far = 0;
+ u->br_near= 1;
+ }
+ /* resolve 3dnow weirdness. */
+ } else if ( u->mnemonic == UD_I3dnow ) {
+ u->mnemonic = ud_itab_list[ ITAB__3DNOW ][ inp_curr( u ) ].mnemonic;
+ }
+ /* SWAPGS is only valid in 64bits mode */
+ if ( u->mnemonic == UD_Iswapgs && u->dis_mode != 64 ) {
+ u->error = 1;
+ return -1;
+ }
+
+ return 0;
+}
+
+
+/* -----------------------------------------------------------------------------
+ * decode_a()- Decodes operands of the type seg:offset
+ * -----------------------------------------------------------------------------
+ */
+static void
+decode_a(struct ud* u, struct ud_operand *op)
+{
+ if (u->opr_mode == 16) {
+ /* seg16:off16 */
+ op->type = UD_OP_PTR;
+ op->size = 32;
+ op->lval.ptr.off = inp_uint16(u);
+ op->lval.ptr.seg = inp_uint16(u);
+ } else {
+ /* seg16:off32 */
+ op->type = UD_OP_PTR;
+ op->size = 48;
+ op->lval.ptr.off = inp_uint32(u);
+ op->lval.ptr.seg = inp_uint16(u);
+ }
+}
+
+/* -----------------------------------------------------------------------------
+ * decode_gpr() - Returns decoded General Purpose Register
+ * -----------------------------------------------------------------------------
+ */
+static enum ud_type
+decode_gpr(register struct ud* u, unsigned int s, unsigned char rm)
+{
+ s = resolve_operand_size(u, s);
+
+ switch (s) {
+ case 64:
+ return UD_R_RAX + rm;
+ case SZ_DP:
+ case 32:
+ return UD_R_EAX + rm;
+ case SZ_WP:
+ case 16:
+ return UD_R_AX + rm;
+ case 8:
+ if (u->dis_mode == 64 && u->pfx_rex) {
+ if (rm >= 4)
+ return UD_R_SPL + (rm-4);
+ return UD_R_AL + rm;
+ } else return UD_R_AL + rm;
+ default:
+ return 0;
+ }
+}
+
+/* -----------------------------------------------------------------------------
+ * resolve_gpr64() - 64bit General Purpose Register-Selection.
+ * -----------------------------------------------------------------------------
+ */
+static enum ud_type
+resolve_gpr64(struct ud* u, enum ud_operand_code gpr_op)
+{
+ if (gpr_op >= OP_rAXr8 && gpr_op <= OP_rDIr15)
+ gpr_op = (gpr_op - OP_rAXr8) | (REX_B(u->pfx_rex) << 3);
+ else gpr_op = (gpr_op - OP_rAX);
+
+ if (u->opr_mode == 16)
+ return gpr_op + UD_R_AX;
+ if (u->dis_mode == 32 ||
+ (u->opr_mode == 32 && ! (REX_W(u->pfx_rex) || u->default64))) {
+ return gpr_op + UD_R_EAX;
+ }
+
+ return gpr_op + UD_R_RAX;
+}
+
+/* -----------------------------------------------------------------------------
+ * resolve_gpr32 () - 32bit General Purpose Register-Selection.
+ * -----------------------------------------------------------------------------
+ */
+static enum ud_type
+resolve_gpr32(struct ud* u, enum ud_operand_code gpr_op)
+{
+ gpr_op = gpr_op - OP_eAX;
+
+ if (u->opr_mode == 16)
+ return gpr_op + UD_R_AX;
+
+ return gpr_op + UD_R_EAX;
+}
+
+/* -----------------------------------------------------------------------------
+ * resolve_reg() - Resolves the register type
+ * -----------------------------------------------------------------------------
+ */
+static enum ud_type
+resolve_reg(struct ud* u, unsigned int type, unsigned char i)
+{
+ switch (type) {
+ case T_MMX : return UD_R_MM0 + (i & 7);
+ case T_XMM : return UD_R_XMM0 + i;
+ case T_CRG : return UD_R_CR0 + i;
+ case T_DBG : return UD_R_DR0 + i;
+ case T_SEG : return UD_R_ES + (i & 7);
+ case T_NONE:
+ default: return UD_NONE;
+ }
+}
+
+/* -----------------------------------------------------------------------------
+ * decode_imm() - Decodes Immediate values.
+ * -----------------------------------------------------------------------------
+ */
+static void
+decode_imm(struct ud* u, unsigned int s, struct ud_operand *op)
+{
+ op->size = resolve_operand_size(u, s);
+ op->type = UD_OP_IMM;
+
+ switch (op->size) {
+ case 8: op->lval.sbyte = inp_uint8(u); break;
+ case 16: op->lval.uword = inp_uint16(u); break;
+ case 32: op->lval.udword = inp_uint32(u); break;
+ case 64: op->lval.uqword = inp_uint64(u); break;
+ default: return;
+ }
+}
+
+/* -----------------------------------------------------------------------------
+ * decode_modrm() - Decodes ModRM Byte
+ * -----------------------------------------------------------------------------
+ */
+static void
+decode_modrm(struct ud* u, struct ud_operand *op, unsigned int s,
+ unsigned char rm_type, struct ud_operand *opreg,
+ unsigned char reg_size, unsigned char reg_type)
+{
+ unsigned char mod, rm, reg;
+
+ inp_next(u);
+
+ /* get mod, r/m and reg fields */
+ mod = MODRM_MOD(inp_curr(u));
+ rm = (REX_B(u->pfx_rex) << 3) | MODRM_RM(inp_curr(u));
+ reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(inp_curr(u));
+
+ op->size = resolve_operand_size(u, s);
+
+ /* if mod is 11b, then the UD_R_m specifies a gpr/mmx/sse/control/debug */
+ if (mod == 3) {
+ op->type = UD_OP_REG;
+ if (rm_type == T_GPR)
+ op->base = decode_gpr(u, op->size, rm);
+ else op->base = resolve_reg(u, rm_type, (REX_B(u->pfx_rex) << 3) | (rm&7));
+ }
+ /* else its memory addressing */
+ else {
+ op->type = UD_OP_MEM;
+
+ /* 64bit addressing */
+ if (u->adr_mode == 64) {
+
+ op->base = UD_R_RAX + rm;
+
+ /* get offset type */
+ if (mod == 1)
+ op->offset = 8;
+ else if (mod == 2)
+ op->offset = 32;
+ else if (mod == 0 && (rm & 7) == 5) {
+ op->base = UD_R_RIP;
+ op->offset = 32;
+ } else op->offset = 0;
+
+ /* Scale-Index-Base (SIB) */
+ if ((rm & 7) == 4) {
+ inp_next(u);
+
+ op->scale = (1 << SIB_S(inp_curr(u))) & ~1;
+ op->index = UD_R_RAX + (SIB_I(inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
+ op->base = UD_R_RAX + (SIB_B(inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
+
+ /* special conditions for base reference */
+ if (op->index == UD_R_RSP) {
+ op->index = UD_NONE;
+ op->scale = UD_NONE;
+ }
+
+ if (op->base == UD_R_RBP || op->base == UD_R_R13) {
+ if (mod == 0)
+ op->base = UD_NONE;
+ if (mod == 1)
+ op->offset = 8;
+ else op->offset = 32;
+ }
+ }
+ }
+
+ /* 32-Bit addressing mode */
+ else if (u->adr_mode == 32) {
+
+ /* get base */
+ op->base = UD_R_EAX + rm;
+
+ /* get offset type */
+ if (mod == 1)
+ op->offset = 8;
+ else if (mod == 2)
+ op->offset = 32;
+ else if (mod == 0 && rm == 5) {
+ op->base = UD_NONE;
+ op->offset = 32;
+ } else op->offset = 0;
+
+ /* Scale-Index-Base (SIB) */
+ if ((rm & 7) == 4) {
+ inp_next(u);
+
+ op->scale = (1 << SIB_S(inp_curr(u))) & ~1;
+ op->index = UD_R_EAX + (SIB_I(inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
+ op->base = UD_R_EAX + (SIB_B(inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
+
+ if (op->index == UD_R_ESP) {
+ op->index = UD_NONE;
+ op->scale = UD_NONE;
+ }
+
+ /* special condition for base reference */
+ if (op->base == UD_R_EBP) {
+ if (mod == 0)
+ op->base = UD_NONE;
+ if (mod == 1)
+ op->offset = 8;
+ else op->offset = 32;
+ }
+ }
+ }
+
+ /* 16bit addressing mode */
+ else {
+ switch (rm) {
+ case 0: op->base = UD_R_BX; op->index = UD_R_SI; break;
+ case 1: op->base = UD_R_BX; op->index = UD_R_DI; break;
+ case 2: op->base = UD_R_BP; op->index = UD_R_SI; break;
+ case 3: op->base = UD_R_BP; op->index = UD_R_DI; break;
+ case 4: op->base = UD_R_SI; break;
+ case 5: op->base = UD_R_DI; break;
+ case 6: op->base = UD_R_BP; break;
+ case 7: op->base = UD_R_BX; break;
+ }
+
+ if (mod == 0 && rm == 6) {
+ op->offset= 16;
+ op->base = UD_NONE;
+ }
+ else if (mod == 1)
+ op->offset = 8;
+ else if (mod == 2)
+ op->offset = 16;
+ }
+ }
+
+ /* extract offset, if any */
+ switch(op->offset) {
+ case 8 : op->lval.ubyte = inp_uint8(u); break;
+ case 16: op->lval.uword = inp_uint16(u); break;
+ case 32: op->lval.udword = inp_uint32(u); break;
+ case 64: op->lval.uqword = inp_uint64(u); break;
+ default: break;
+ }
+
+ /* resolve register encoded in reg field */
+ if (opreg) {
+ opreg->type = UD_OP_REG;
+ opreg->size = resolve_operand_size(u, reg_size);
+ if (reg_type == T_GPR)
+ opreg->base = decode_gpr(u, opreg->size, reg);
+ else opreg->base = resolve_reg(u, reg_type, reg);
+ }
+}
+
+/* -----------------------------------------------------------------------------
+ * decode_o() - Decodes offset
+ * -----------------------------------------------------------------------------
+ */
+static void
+decode_o(struct ud* u, unsigned int s, struct ud_operand *op)
+{
+ switch (u->adr_mode) {
+ case 64:
+ op->offset = 64;
+ op->lval.uqword = inp_uint64(u);
+ break;
+ case 32:
+ op->offset = 32;
+ op->lval.udword = inp_uint32(u);
+ break;
+ case 16:
+ op->offset = 16;
+ op->lval.uword = inp_uint16(u);
+ break;
+ default:
+ return;
+ }
+ op->type = UD_OP_MEM;
+ op->size = resolve_operand_size(u, s);
+}
+
+/* -----------------------------------------------------------------------------
+ * disasm_operands() - Disassembles Operands.
+ * -----------------------------------------------------------------------------
+ */
+static int disasm_operands(register struct ud* u)
+{
+
+
+ /* mopXt = map entry, operand X, type; */
+ enum ud_operand_code mop1t = u->itab_entry->operand1.type;
+ enum ud_operand_code mop2t = u->itab_entry->operand2.type;
+ enum ud_operand_code mop3t = u->itab_entry->operand3.type;
+
+ /* mopXs = map entry, operand X, size */
+ unsigned int mop1s = u->itab_entry->operand1.size;
+ unsigned int mop2s = u->itab_entry->operand2.size;
+ unsigned int mop3s = u->itab_entry->operand3.size;
+
+ /* iop = instruction operand */
+ register struct ud_operand* iop = u->operand;
+
+ switch(mop1t) {
+
+ case OP_A :
+ decode_a(u, &(iop[0]));
+ break;
+
+ /* M[b] ... */
+ case OP_M :
+ if (MODRM_MOD(inp_peek(u)) == 3)
+ u->error= 1;
+ /* E, G/P/V/I/CL/1/S */
+ case OP_E :
+ if (mop2t == OP_G) {
+ decode_modrm(u, &(iop[0]), mop1s, T_GPR, &(iop[1]), mop2s, T_GPR);
+ if (mop3t == OP_I)
+ decode_imm(u, mop3s, &(iop[2]));
+ else if (mop3t == OP_CL) {
+ iop[2].type = UD_OP_REG;
+ iop[2].base = UD_R_CL;
+ iop[2].size = 8;
+ }
+ }
+ else if (mop2t == OP_P)
+ decode_modrm(u, &(iop[0]), mop1s, T_GPR, &(iop[1]), mop2s, T_MMX);
+ else if (mop2t == OP_V)
+ decode_modrm(u, &(iop[0]), mop1s, T_GPR, &(iop[1]), mop2s, T_XMM);
+ else if (mop2t == OP_S)
+ decode_modrm(u, &(iop[0]), mop1s, T_GPR, &(iop[1]), mop2s, T_SEG);
+ else {
+ decode_modrm(u, &(iop[0]), mop1s, T_GPR, NULL, 0, T_NONE);
+ if (mop2t == OP_CL) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = UD_R_CL;
+ iop[1].size = 8;
+ } else if (mop2t == OP_I1) {
+ iop[1].type = UD_OP_CONST;
+ u->operand[1].lval.udword = 1;
+ } else if (mop2t == OP_I) {
+ decode_imm(u, mop2s, &(iop[1]));
+ }
+ }
+ break;
+
+ /* G, E/PR[,I]/VR */
+ case OP_G :
+ if (mop2t == OP_M) {
+ if (MODRM_MOD(inp_peek(u)) == 3)
+ u->error= 1;
+ decode_modrm(u, &(iop[1]), mop2s, T_GPR, &(iop[0]), mop1s, T_GPR);
+ } else if (mop2t == OP_E) {
+ decode_modrm(u, &(iop[1]), mop2s, T_GPR, &(iop[0]), mop1s, T_GPR);
+ if (mop3t == OP_I)
+ decode_imm(u, mop3s, &(iop[2]));
+ } else if (mop2t == OP_PR) {
+ decode_modrm(u, &(iop[1]), mop2s, T_MMX, &(iop[0]), mop1s, T_GPR);
+ if (mop3t == OP_I)
+ decode_imm(u, mop3s, &(iop[2]));
+ } else if (mop2t == OP_VR) {
+ if (MODRM_MOD(inp_peek(u)) != 3)
+ u->error = 1;
+ decode_modrm(u, &(iop[1]), mop2s, T_XMM, &(iop[0]), mop1s, T_GPR);
+ } else if (mop2t == OP_W)
+ decode_modrm(u, &(iop[1]), mop2s, T_XMM, &(iop[0]), mop1s, T_GPR);
+ break;
+
+ /* AL..BH, I/O/DX */
+ case OP_AL : case OP_CL : case OP_DL : case OP_BL :
+ case OP_AH : case OP_CH : case OP_DH : case OP_BH :
+
+ iop[0].type = UD_OP_REG;
+ iop[0].base = UD_R_AL + (mop1t - OP_AL);
+ iop[0].size = 8;
+
+ if (mop2t == OP_I)
+ decode_imm(u, mop2s, &(iop[1]));
+ else if (mop2t == OP_DX) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = UD_R_DX;
+ iop[1].size = 16;
+ }
+ else if (mop2t == OP_O)
+ decode_o(u, mop2s, &(iop[1]));
+ break;
+
+ /* rAX[r8]..rDI[r15], I/rAX..rDI/O */
+ case OP_rAXr8 : case OP_rCXr9 : case OP_rDXr10 : case OP_rBXr11 :
+ case OP_rSPr12: case OP_rBPr13: case OP_rSIr14 : case OP_rDIr15 :
+ case OP_rAX : case OP_rCX : case OP_rDX : case OP_rBX :
+ case OP_rSP : case OP_rBP : case OP_rSI : case OP_rDI :
+
+ iop[0].type = UD_OP_REG;
+ iop[0].base = resolve_gpr64(u, mop1t);
+
+ if (mop2t == OP_I)
+ decode_imm(u, mop2s, &(iop[1]));
+ else if (mop2t >= OP_rAX && mop2t <= OP_rDI) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = resolve_gpr64(u, mop2t);
+ }
+ else if (mop2t == OP_O) {
+ decode_o(u, mop2s, &(iop[1]));
+ iop[0].size = resolve_operand_size(u, mop2s);
+ }
+ break;
+
+ /* AL[r8b]..BH[r15b], I */
+ case OP_ALr8b : case OP_CLr9b : case OP_DLr10b : case OP_BLr11b :
+ case OP_AHr12b: case OP_CHr13b: case OP_DHr14b : case OP_BHr15b :
+ {
+ ud_type_t gpr = (mop1t - OP_ALr8b) + UD_R_AL +
+ (REX_B(u->pfx_rex) << 3);
+ if (UD_R_AH <= gpr && u->pfx_rex)
+ gpr = gpr + 4;
+ iop[0].type = UD_OP_REG;
+ iop[0].base = gpr;
+ if (mop2t == OP_I)
+ decode_imm(u, mop2s, &(iop[1]));
+ break;
+ }
+
+ /* eAX..eDX, DX/I */
+ case OP_eAX : case OP_eCX : case OP_eDX : case OP_eBX :
+ case OP_eSP : case OP_eBP : case OP_eSI : case OP_eDI :
+ iop[0].type = UD_OP_REG;
+ iop[0].base = resolve_gpr32(u, mop1t);
+ if (mop2t == OP_DX) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = UD_R_DX;
+ iop[1].size = 16;
+ } else if (mop2t == OP_I)
+ decode_imm(u, mop2s, &(iop[1]));
+ break;
+
+ /* ES..GS */
+ case OP_ES : case OP_CS : case OP_DS :
+ case OP_SS : case OP_FS : case OP_GS :
+
+ /* in 64bits mode, only fs and gs are allowed */
+ if (u->dis_mode == 64)
+ if (mop1t != OP_FS && mop1t != OP_GS)
+ u->error= 1;
+ iop[0].type = UD_OP_REG;
+ iop[0].base = (mop1t - OP_ES) + UD_R_ES;
+ iop[0].size = 16;
+
+ break;
+
+ /* J */
+ case OP_J :
+ decode_imm(u, mop1s, &(iop[0]));
+ iop[0].type = UD_OP_JIMM;
+ break ;
+
+ /* PR, I */
+ case OP_PR:
+ if (MODRM_MOD(inp_peek(u)) != 3)
+ u->error = 1;
+ decode_modrm(u, &(iop[0]), mop1s, T_MMX, NULL, 0, T_NONE);
+ if (mop2t == OP_I)
+ decode_imm(u, mop2s, &(iop[1]));
+ break;
+
+ /* VR, I */
+ case OP_VR:
+ if (MODRM_MOD(inp_peek(u)) != 3)
+ u->error = 1;
+ decode_modrm(u, &(iop[0]), mop1s, T_XMM, NULL, 0, T_NONE);
+ if (mop2t == OP_I)
+ decode_imm(u, mop2s, &(iop[1]));
+ break;
+
+ /* P, Q[,I]/W/E[,I],VR */
+ case OP_P :
+ if (mop2t == OP_Q) {
+ decode_modrm(u, &(iop[1]), mop2s, T_MMX, &(iop[0]), mop1s, T_MMX);
+ if (mop3t == OP_I)
+ decode_imm(u, mop3s, &(iop[2]));
+ } else if (mop2t == OP_W) {
+ decode_modrm(u, &(iop[1]), mop2s, T_XMM, &(iop[0]), mop1s, T_MMX);
+ } else if (mop2t == OP_VR) {
+ if (MODRM_MOD(inp_peek(u)) != 3)
+ u->error = 1;
+ decode_modrm(u, &(iop[1]), mop2s, T_XMM, &(iop[0]), mop1s, T_MMX);
+ } else if (mop2t == OP_E) {
+ decode_modrm(u, &(iop[1]), mop2s, T_GPR, &(iop[0]), mop1s, T_MMX);
+ if (mop3t == OP_I)
+ decode_imm(u, mop3s, &(iop[2]));
+ }
+ break;
+
+ /* R, C/D */
+ case OP_R :
+ if (mop2t == OP_C)
+ decode_modrm(u, &(iop[0]), mop1s, T_GPR, &(iop[1]), mop2s, T_CRG);
+ else if (mop2t == OP_D)
+ decode_modrm(u, &(iop[0]), mop1s, T_GPR, &(iop[1]), mop2s, T_DBG);
+ break;
+
+ /* C, R */
+ case OP_C :
+ decode_modrm(u, &(iop[1]), mop2s, T_GPR, &(iop[0]), mop1s, T_CRG);
+ break;
+
+ /* D, R */
+ case OP_D :
+ decode_modrm(u, &(iop[1]), mop2s, T_GPR, &(iop[0]), mop1s, T_DBG);
+ break;
+
+ /* Q, P */
+ case OP_Q :
+ decode_modrm(u, &(iop[0]), mop1s, T_MMX, &(iop[1]), mop2s, T_MMX);
+ break;
+
+ /* S, E */
+ case OP_S :
+ decode_modrm(u, &(iop[1]), mop2s, T_GPR, &(iop[0]), mop1s, T_SEG);
+ break;
+
+ /* W, V */
+ case OP_W :
+ decode_modrm(u, &(iop[0]), mop1s, T_XMM, &(iop[1]), mop2s, T_XMM);
+ break;
+
+ /* V, W[,I]/Q/M/E */
+ case OP_V :
+ if (mop2t == OP_W) {
+ /* special cases for movlps and movhps */
+ if (MODRM_MOD(inp_peek(u)) == 3) {
+ if (u->mnemonic == UD_Imovlps)
+ u->mnemonic = UD_Imovhlps;
+ else
+ if (u->mnemonic == UD_Imovhps)
+ u->mnemonic = UD_Imovlhps;
+ }
+ decode_modrm(u, &(iop[1]), mop2s, T_XMM, &(iop[0]), mop1s, T_XMM);
+ if (mop3t == OP_I)
+ decode_imm(u, mop3s, &(iop[2]));
+ } else if (mop2t == OP_Q)
+ decode_modrm(u, &(iop[1]), mop2s, T_MMX, &(iop[0]), mop1s, T_XMM);
+ else if (mop2t == OP_M) {
+ if (MODRM_MOD(inp_peek(u)) == 3)
+ u->error= 1;
+ decode_modrm(u, &(iop[1]), mop2s, T_GPR, &(iop[0]), mop1s, T_XMM);
+ } else if (mop2t == OP_E) {
+ decode_modrm(u, &(iop[1]), mop2s, T_GPR, &(iop[0]), mop1s, T_XMM);
+ } else if (mop2t == OP_PR) {
+ decode_modrm(u, &(iop[1]), mop2s, T_MMX, &(iop[0]), mop1s, T_XMM);
+ }
+ break;
+
+ /* DX, eAX/AL */
+ case OP_DX :
+ iop[0].type = UD_OP_REG;
+ iop[0].base = UD_R_DX;
+ iop[0].size = 16;
+
+ if (mop2t == OP_eAX) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = resolve_gpr32(u, mop2t);
+ } else if (mop2t == OP_AL) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = UD_R_AL;
+ iop[1].size = 8;
+ }
+
+ break;
+
+ /* I, I/AL/eAX */
+ case OP_I :
+ decode_imm(u, mop1s, &(iop[0]));
+ if (mop2t == OP_I)
+ decode_imm(u, mop2s, &(iop[1]));
+ else if (mop2t == OP_AL) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = UD_R_AL;
+ iop[1].size = 16;
+ } else if (mop2t == OP_eAX) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = resolve_gpr32(u, mop2t);
+ }
+ break;
+
+ /* O, AL/eAX */
+ case OP_O :
+ decode_o(u, mop1s, &(iop[0]));
+ iop[1].type = UD_OP_REG;
+ iop[1].size = resolve_operand_size(u, mop1s);
+ if (mop2t == OP_AL)
+ iop[1].base = UD_R_AL;
+ else if (mop2t == OP_eAX)
+ iop[1].base = resolve_gpr32(u, mop2t);
+ else if (mop2t == OP_rAX)
+ iop[1].base = resolve_gpr64(u, mop2t);
+ break;
+
+ /* 3 */
+ case OP_I3 :
+ iop[0].type = UD_OP_CONST;
+ iop[0].lval.sbyte = 3;
+ break;
+
+ /* ST(n), ST(n) */
+ case OP_ST0 : case OP_ST1 : case OP_ST2 : case OP_ST3 :
+ case OP_ST4 : case OP_ST5 : case OP_ST6 : case OP_ST7 :
+
+ iop[0].type = UD_OP_REG;
+ iop[0].base = (mop1t-OP_ST0) + UD_R_ST0;
+ iop[0].size = 0;
+
+ if (mop2t >= OP_ST0 && mop2t <= OP_ST7) {
+ iop[1].type = UD_OP_REG;
+ iop[1].base = (mop2t-OP_ST0) + UD_R_ST0;
+ iop[1].size = 0;
+ }
+ break;
+
+ /* AX */
+ case OP_AX:
+ iop[0].type = UD_OP_REG;
+ iop[0].base = UD_R_AX;
+ iop[0].size = 16;
+ break;
+
+ /* none */
+ default :
+ iop[0].type = iop[1].type = iop[2].type = UD_NONE;
+ }
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * clear_insn() - clear instruction pointer
+ * -----------------------------------------------------------------------------
+ */
+static int clear_insn(register struct ud* u)
+{
+ u->error = 0;
+ u->pfx_seg = 0;
+ u->pfx_opr = 0;
+ u->pfx_adr = 0;
+ u->pfx_lock = 0;
+ u->pfx_repne = 0;
+ u->pfx_rep = 0;
+ u->pfx_repe = 0;
+ u->pfx_seg = 0;
+ u->pfx_rex = 0;
+ u->pfx_insn = 0;
+ u->mnemonic = UD_Inone;
+ u->itab_entry = NULL;
+
+ memset( &u->operand[ 0 ], 0, sizeof( struct ud_operand ) );
+ memset( &u->operand[ 1 ], 0, sizeof( struct ud_operand ) );
+ memset( &u->operand[ 2 ], 0, sizeof( struct ud_operand ) );
+
+ return 0;
+}
+
+static int do_mode( struct ud* u )
+{
+ /* if in error state, bail out */
+ if ( u->error ) return -1;
+
+ /* propagate perfix effects */
+ if ( u->dis_mode == 64 ) { /* set 64bit-mode flags */
+
+ /* Check validity of instruction m64 */
+ if ( P_INV64( u->itab_entry->prefix ) ) {
+ u->error = 1;
+ return -1;
+ }
+
+ /* effective rex prefix is the effective mask for the
+ * instruction hard-coded in the opcode map.
+ */
+ u->pfx_rex = ( u->pfx_rex & 0x40 ) |
+ ( u->pfx_rex & REX_PFX_MASK( u->itab_entry->prefix ) );
+
+ /* whether this instruction has a default operand size of
+ * 64bit, also hardcoded into the opcode map.
+ */
+ u->default64 = P_DEF64( u->itab_entry->prefix );
+ /* calculate effective operand size */
+ if ( REX_W( u->pfx_rex ) ) {
+ u->opr_mode = 64;
+ } else if ( u->pfx_opr ) {
+ u->opr_mode = 16;
+ } else {
+ /* unless the default opr size of instruction is 64,
+ * the effective operand size in the absence of rex.w
+ * prefix is 32.
+ */
+ u->opr_mode = ( u->default64 ) ? 64 : 32;
+ }
+
+ /* calculate effective address size */
+ u->adr_mode = (u->pfx_adr) ? 32 : 64;
+ } else if ( u->dis_mode == 32 ) { /* set 32bit-mode flags */
+ u->opr_mode = ( u->pfx_opr ) ? 16 : 32;
+ u->adr_mode = ( u->pfx_adr ) ? 16 : 32;
+ } else if ( u->dis_mode == 16 ) { /* set 16bit-mode flags */
+ u->opr_mode = ( u->pfx_opr ) ? 32 : 16;
+ u->adr_mode = ( u->pfx_adr ) ? 32 : 16;
+ }
+
+ /* These flags determine which operand to apply the operand size
+ * cast to.
+ */
+ u->c1 = ( P_C1( u->itab_entry->prefix ) ) ? 1 : 0;
+ u->c2 = ( P_C2( u->itab_entry->prefix ) ) ? 1 : 0;
+ u->c3 = ( P_C3( u->itab_entry->prefix ) ) ? 1 : 0;
+
+ /* set flags for implicit addressing */
+ u->implicit_addr = P_IMPADDR( u->itab_entry->prefix );
+
+ return 0;
+}
+
+static int gen_hex( struct ud *u )
+{
+ unsigned int i;
+ unsigned char *src_ptr = inp_sess( u );
+ char* src_hex;
+
+ /* bail out if in error stat. */
+ if ( u->error ) return -1;
+ /* output buffer pointe */
+ src_hex = ( char* ) u->insn_hexcode;
+ /* for each byte used to decode instruction */
+ for ( i = 0; i < u->inp_ctr; ++i, ++src_ptr) {
+ sprintf( src_hex, "%02x", *src_ptr & 0xFF );
+ src_hex += 2;
+ }
+ return 0;
+}
+
+/* =============================================================================
+ * ud_decode() - Instruction decoder. Returns the number of bytes decoded.
+ * =============================================================================
+ */
+unsigned int ud_decode( struct ud* u )
+{
+ inp_start(u);
+
+ if ( clear_insn( u ) ) {
+ ; /* error */
+ } else if ( get_prefixes( u ) != 0 ) {
+ ; /* error */
+ } else if ( search_itab( u ) != 0 ) {
+ ; /* error */
+ } else if ( do_mode( u ) != 0 ) {
+ ; /* error */
+ } else if ( disasm_operands( u ) != 0 ) {
+ ; /* error */
+ } else if ( resolve_mnemonic( u ) != 0 ) {
+ ; /* error */
+ }
+
+ /* Handle decode error. */
+ if ( u->error ) {
+ /* clear out the decode data. */
+ clear_insn( u );
+ /* mark the sequence of bytes as invalid. */
+ u->itab_entry = & ie_invalid;
+ u->mnemonic = u->itab_entry->mnemonic;
+ }
+
+ u->insn_offset = u->pc; /* set offset of instruction */
+ u->insn_fill = 0; /* set translation buffer index to 0 */
+ u->pc += u->inp_ctr; /* move program counter by bytes decoded */
+ gen_hex( u ); /* generate hex code */
+
+ /* return number of bytes disassembled. */
+ return u->inp_ctr;
+}
+
+/* vim:cindent
+ * vim:ts=4
+ * vim:sw=4
+ * vim:expandtab
+ */
--- /dev/null
+/* udis86 - libudis86/decode.h
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef UD_DECODE_H
+#define UD_DECODE_H
+
+#define MAX_INSN_LENGTH 15
+
+/* register classes */
+#define T_NONE 0
+#define T_GPR 1
+#define T_MMX 2
+#define T_CRG 3
+#define T_DBG 4
+#define T_SEG 5
+#define T_XMM 6
+
+/* itab prefix bits */
+#define P_none ( 0 )
+#define P_c1 ( 1 << 0 )
+#define P_C1(n) ( ( n >> 0 ) & 1 )
+#define P_rexb ( 1 << 1 )
+#define P_REXB(n) ( ( n >> 1 ) & 1 )
+#define P_depM ( 1 << 2 )
+#define P_DEPM(n) ( ( n >> 2 ) & 1 )
+#define P_c3 ( 1 << 3 )
+#define P_C3(n) ( ( n >> 3 ) & 1 )
+#define P_inv64 ( 1 << 4 )
+#define P_INV64(n) ( ( n >> 4 ) & 1 )
+#define P_rexw ( 1 << 5 )
+#define P_REXW(n) ( ( n >> 5 ) & 1 )
+#define P_c2 ( 1 << 6 )
+#define P_C2(n) ( ( n >> 6 ) & 1 )
+#define P_def64 ( 1 << 7 )
+#define P_DEF64(n) ( ( n >> 7 ) & 1 )
+#define P_rexr ( 1 << 8 )
+#define P_REXR(n) ( ( n >> 8 ) & 1 )
+#define P_oso ( 1 << 9 )
+#define P_OSO(n) ( ( n >> 9 ) & 1 )
+#define P_aso ( 1 << 10 )
+#define P_ASO(n) ( ( n >> 10 ) & 1 )
+#define P_rexx ( 1 << 11 )
+#define P_REXX(n) ( ( n >> 11 ) & 1 )
+#define P_ImpAddr ( 1 << 12 )
+#define P_IMPADDR(n) ( ( n >> 12 ) & 1 )
+
+/* rex prefix bits */
+#define REX_W(r) ( ( 0xF & ( r ) ) >> 3 )
+#define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 )
+#define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 )
+#define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 )
+#define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \
+ ( P_REXR(n) << 2 ) | \
+ ( P_REXX(n) << 1 ) | \
+ ( P_REXB(n) << 0 ) )
+
+/* scable-index-base bits */
+#define SIB_S(b) ( ( b ) >> 6 )
+#define SIB_I(b) ( ( ( b ) >> 3 ) & 7 )
+#define SIB_B(b) ( ( b ) & 7 )
+
+/* modrm bits */
+#define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 )
+#define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 )
+#define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 )
+#define MODRM_RM(b) ( ( b ) & 7 )
+
+/* operand type constants -- order is important! */
+
+enum __attribute__((packed)) ud_operand_code {
+ OP_NONE,
+
+ OP_A, OP_E, OP_M, OP_G,
+ OP_I,
+
+ OP_AL, OP_CL, OP_DL, OP_BL,
+ OP_AH, OP_CH, OP_DH, OP_BH,
+
+ OP_ALr8b, OP_CLr9b, OP_DLr10b, OP_BLr11b,
+ OP_AHr12b, OP_CHr13b, OP_DHr14b, OP_BHr15b,
+
+ OP_AX, OP_CX, OP_DX, OP_BX,
+ OP_SI, OP_DI, OP_SP, OP_BP,
+
+ OP_rAX, OP_rCX, OP_rDX, OP_rBX,
+ OP_rSP, OP_rBP, OP_rSI, OP_rDI,
+
+ OP_rAXr8, OP_rCXr9, OP_rDXr10, OP_rBXr11,
+ OP_rSPr12, OP_rBPr13, OP_rSIr14, OP_rDIr15,
+
+ OP_eAX, OP_eCX, OP_eDX, OP_eBX,
+ OP_eSP, OP_eBP, OP_eSI, OP_eDI,
+
+ OP_ES, OP_CS, OP_SS, OP_DS,
+ OP_FS, OP_GS,
+
+ OP_ST0, OP_ST1, OP_ST2, OP_ST3,
+ OP_ST4, OP_ST5, OP_ST6, OP_ST7,
+
+ OP_J, OP_S, OP_O,
+ OP_I1, OP_I3,
+
+ OP_V, OP_W, OP_Q, OP_P,
+
+ OP_R, OP_C, OP_D, OP_VR, OP_PR
+};
+
+
+/* operand size constants */
+
+enum __attribute__((packed)) ud_operand_size {
+ SZ_NA = 0,
+ SZ_Z = 1,
+ SZ_V = 2,
+ SZ_P = 3,
+ SZ_WP = 4,
+ SZ_DP = 5,
+ SZ_MDQ = 6,
+ SZ_RDQ = 7,
+
+ /* the following values are used as is,
+ * and thus hard-coded. changing them
+ * will break internals
+ */
+ SZ_B = 8,
+ SZ_W = 16,
+ SZ_D = 32,
+ SZ_Q = 64,
+ SZ_T = 80,
+ SZ_O = 128,
+};
+
+
+/* A single operand of an entry in the instruction table.
+ * (internal use only)
+ */
+struct ud_itab_entry_operand
+{
+ enum ud_operand_code type;
+ enum ud_operand_size size;
+};
+
+
+/* A single entry in an instruction table.
+ *(internal use only)
+ */
+struct ud_itab_entry
+{
+ enum ud_mnemonic_code mnemonic;
+ struct ud_itab_entry_operand operand1;
+ struct ud_itab_entry_operand operand2;
+ struct ud_itab_entry_operand operand3;
+ uint32_t prefix;
+};
+
+extern const char * ud_lookup_mnemonic( enum ud_mnemonic_code c );
+
+#endif /* UD_DECODE_H */
+
+/* vim:cindent
+ * vim:expandtab
+ * vim:ts=4
+ * vim:sw=4
+ */
--- /dev/null
+/* udis86 - libudis86/extern.h
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef UD_EXTERN_H
+#define UD_EXTERN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "types.h"
+
+/* ============================= PUBLIC API ================================= */
+
+extern void ud_init(struct ud*);
+
+extern void ud_set_mode(struct ud*, uint8_t);
+
+extern void ud_set_pc(struct ud*, uint64_t);
+
+extern void ud_set_input_hook(struct ud*, int (*)(struct ud*));
+
+extern void ud_set_input_buffer(struct ud*, uint8_t*, size_t);
+
+#ifndef __UD_STANDALONE__
+extern void ud_set_input_file(struct ud*, FILE*);
+#endif /* __UD_STANDALONE__ */
+
+extern void ud_set_vendor(struct ud*, unsigned);
+
+extern void ud_set_syntax(struct ud*, void (*)(struct ud*));
+
+extern void ud_input_skip(struct ud*, size_t);
+
+extern int ud_input_end(struct ud*);
+
+extern unsigned int ud_decode(struct ud*);
+
+extern unsigned int ud_disassemble(struct ud*);
+
+extern void ud_translate_intel(struct ud*);
+
+extern void ud_translate_att(struct ud*);
+
+extern char* ud_insn_asm(struct ud* u);
+
+extern uint8_t* ud_insn_ptr(struct ud* u);
+
+extern uint64_t ud_insn_off(struct ud*);
+
+extern char* ud_insn_hex(struct ud*);
+
+extern unsigned int ud_insn_len(struct ud* u);
+
+extern const char* ud_lookup_mnemonic(enum ud_mnemonic_code c);
+
+extern void ud_set_user_opaque_data(struct ud*, void*);
+
+extern void *ud_get_user_opaque_data(struct ud*);
+
+/* ========================================================================== */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null
+/* udis86 - libudis86/input.c
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "extern.h"
+#include "types.h"
+#include "input.h"
+
+/* -----------------------------------------------------------------------------
+ * inp_buff_hook() - Hook for buffered inputs.
+ * -----------------------------------------------------------------------------
+ */
+static int
+inp_buff_hook(struct ud* u)
+{
+ if (u->inp_buff < u->inp_buff_end)
+ return *u->inp_buff++;
+ else return -1;
+}
+
+#ifndef __UD_STANDALONE__
+/* -----------------------------------------------------------------------------
+ * inp_file_hook() - Hook for FILE inputs.
+ * -----------------------------------------------------------------------------
+ */
+static int
+inp_file_hook(struct ud* u)
+{
+ return fgetc(u->inp_file);
+}
+#endif /* __UD_STANDALONE__*/
+
+/* =============================================================================
+ * ud_inp_set_hook() - Sets input hook.
+ * =============================================================================
+ */
+extern void
+ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*))
+{
+ u->inp_hook = hook;
+ inp_init(u);
+}
+
+extern void
+ud_set_user_opaque_data( struct ud * u, void * opaque )
+{
+ u->user_opaque_data = opaque;
+}
+
+extern void *
+ud_get_user_opaque_data( struct ud * u )
+{
+ return u->user_opaque_data;
+}
+
+/* =============================================================================
+ * ud_inp_set_buffer() - Set buffer as input.
+ * =============================================================================
+ */
+extern void
+ud_set_input_buffer(register struct ud* u, uint8_t* buf, size_t len)
+{
+ u->inp_hook = inp_buff_hook;
+ u->inp_buff = buf;
+ u->inp_buff_end = buf + len;
+ inp_init(u);
+}
+
+#ifndef __UD_STANDALONE__
+/* =============================================================================
+ * ud_input_set_file() - Set buffer as input.
+ * =============================================================================
+ */
+extern void
+ud_set_input_file(register struct ud* u, FILE* f)
+{
+ u->inp_hook = inp_file_hook;
+ u->inp_file = f;
+ inp_init(u);
+}
+#endif /* __UD_STANDALONE__ */
+
+/* =============================================================================
+ * ud_input_skip() - Skip n input bytes.
+ * =============================================================================
+ */
+extern void
+ud_input_skip(struct ud* u, size_t n)
+{
+ while (n--) {
+ u->inp_hook(u);
+ }
+}
+
+/* =============================================================================
+ * ud_input_end() - Test for end of input.
+ * =============================================================================
+ */
+extern int
+ud_input_end(struct ud* u)
+{
+ return (u->inp_curr == u->inp_fill) && u->inp_end;
+}
+
+/* -----------------------------------------------------------------------------
+ * inp_next() - Loads and returns the next byte from input.
+ *
+ * inp_curr and inp_fill are pointers to the cache. The program is written based
+ * on the property that they are 8-bits in size, and will eventually wrap around
+ * forming a circular buffer. So, the size of the cache is 256 in size, kind of
+ * unnecessary yet optimized.
+ *
+ * A buffer inp_sess stores the bytes disassembled for a single session.
+ * -----------------------------------------------------------------------------
+ */
+extern uint8_t inp_next(struct ud* u)
+{
+ int c = -1;
+ /* if current pointer is not upto the fill point in the
+ * input cache.
+ */
+ if ( u->inp_curr != u->inp_fill ) {
+ c = u->inp_cache[ ++u->inp_curr ];
+ /* if !end-of-input, call the input hook and get a byte */
+ } else if ( u->inp_end || ( c = u->inp_hook( u ) ) == -1 ) {
+ /* end-of-input, mark it as an error, since the decoder,
+ * expected a byte more.
+ */
+ u->error = 1;
+ /* flag end of input */
+ u->inp_end = 1;
+ return 0;
+ } else {
+ /* increment pointers, we have a new byte. */
+ u->inp_curr = ++u->inp_fill;
+ /* add the byte to the cache */
+ u->inp_cache[ u->inp_fill ] = c;
+ }
+ /* record bytes input per decode-session. */
+ u->inp_sess[ u->inp_ctr++ ] = c;
+ /* return byte */
+ return ( uint8_t ) c;
+}
+
+/* -----------------------------------------------------------------------------
+ * inp_back() - Move back a single byte in the stream.
+ * -----------------------------------------------------------------------------
+ */
+extern void
+inp_back(struct ud* u)
+{
+ if ( u->inp_ctr > 0 ) {
+ --u->inp_curr;
+ --u->inp_ctr;
+ }
+}
+
+/* -----------------------------------------------------------------------------
+ * inp_peek() - Peek into the next byte in source.
+ * -----------------------------------------------------------------------------
+ */
+extern uint8_t
+inp_peek(struct ud* u)
+{
+ uint8_t r = inp_next(u);
+ if ( !u->error ) inp_back(u); /* Don't backup if there was an error */
+ return r;
+}
+
+/* -----------------------------------------------------------------------------
+ * inp_move() - Move ahead n input bytes.
+ * -----------------------------------------------------------------------------
+ */
+extern void
+inp_move(struct ud* u, size_t n)
+{
+ while (n--)
+ inp_next(u);
+}
+
+/*------------------------------------------------------------------------------
+ * inp_uintN() - return uintN from source.
+ *------------------------------------------------------------------------------
+ */
+extern uint8_t
+inp_uint8(struct ud* u)
+{
+ return inp_next(u);
+}
+
+extern uint16_t
+inp_uint16(struct ud* u)
+{
+ uint16_t r, ret;
+
+ ret = inp_next(u);
+ r = inp_next(u);
+ return ret | (r << 8);
+}
+
+extern uint32_t
+inp_uint32(struct ud* u)
+{
+ uint32_t r, ret;
+
+ ret = inp_next(u);
+ r = inp_next(u);
+ ret = ret | (r << 8);
+ r = inp_next(u);
+ ret = ret | (r << 16);
+ r = inp_next(u);
+ return ret | (r << 24);
+}
+
+extern uint64_t
+inp_uint64(struct ud* u)
+{
+ uint64_t r, ret;
+
+ ret = inp_next(u);
+ r = inp_next(u);
+ ret = ret | (r << 8);
+ r = inp_next(u);
+ ret = ret | (r << 16);
+ r = inp_next(u);
+ ret = ret | (r << 24);
+ r = inp_next(u);
+ ret = ret | (r << 32);
+ r = inp_next(u);
+ ret = ret | (r << 40);
+ r = inp_next(u);
+ ret = ret | (r << 48);
+ r = inp_next(u);
+ return ret | (r << 56);
+}
--- /dev/null
+/* udis86 - libudis86/input.h
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef UD_INPUT_H
+#define UD_INPUT_H
+
+#include "types.h"
+
+uint8_t inp_next(struct ud*);
+uint8_t inp_peek(struct ud*);
+uint8_t inp_uint8(struct ud*);
+uint16_t inp_uint16(struct ud*);
+uint32_t inp_uint32(struct ud*);
+uint64_t inp_uint64(struct ud*);
+void inp_move(struct ud*, size_t);
+void inp_back(struct ud*);
+
+/* inp_init() - Initializes the input system. */
+#define inp_init(u) \
+do { \
+ u->inp_curr = 0; \
+ u->inp_fill = 0; \
+ u->inp_ctr = 0; \
+ u->inp_end = 0; \
+} while (0)
+
+/* inp_start() - Should be called before each de-code operation. */
+#define inp_start(u) u->inp_ctr = 0
+
+/* inp_back() - Resets the current pointer to its position before the current
+ * instruction disassembly was started.
+ */
+#define inp_reset(u) \
+do { \
+ u->inp_curr -= u->inp_ctr; \
+ u->inp_ctr = 0; \
+} while (0)
+
+/* inp_sess() - Returns the pointer to current session. */
+#define inp_sess(u) (u->inp_sess)
+
+/* inp_cur() - Returns the current input byte. */
+#define inp_curr(u) ((u)->inp_cache[(u)->inp_curr])
+
+#endif
--- /dev/null
+#!/usr/bin/env python
+
+import os
+import sys
+import string
+from xml.dom import minidom
+
+#
+# opgen.py -- generates tables and constants for decoding
+#
+# - itab.c
+# - itab.h
+#
+
+#
+# special mnemonic types for internal purposes.
+#
+spl_mnm_types = [ 'd3vil', \
+ 'na', \
+ 'grp_reg', \
+ 'grp_rm', \
+ 'grp_vendor', \
+ 'grp_x87', \
+ 'grp_mode', \
+ 'grp_osize', \
+ 'grp_asize', \
+ 'grp_mod', \
+ 'grp_3byte', \
+ 'none' \
+ ]
+
+#
+# opcode-vendor dictionary
+#
+vend_dict = {
+ 'AMD' : '00',
+ 'INTEL' : '01',
+ 'ANY' : '02'
+}
+
+
+#
+# opcode-mode dictionary
+#
+
+mode_dict = {
+ '16' : '00',
+ '32' : '01',
+ '64' : '02'
+}
+
+#
+# opcode-operand dictionary
+#
+operand_dict = {
+ "Ap" : [ "OP_A" , "SZ_P" ],
+ "E" : [ "OP_E" , "SZ_NA" ],
+ "Eb" : [ "OP_E" , "SZ_B" ],
+ "Ew" : [ "OP_E" , "SZ_W" ],
+ "Ev" : [ "OP_E" , "SZ_V" ],
+ "Ed" : [ "OP_E" , "SZ_D" ],
+ "Eq" : [ "OP_E" , "SZ_Q" ],
+ "Ez" : [ "OP_E" , "SZ_Z" ],
+ "Ex" : [ "OP_E" , "SZ_MDQ" ],
+ "Ep" : [ "OP_E" , "SZ_P" ],
+ "G" : [ "OP_G" , "SZ_NA" ],
+ "Gb" : [ "OP_G" , "SZ_B" ],
+ "Gw" : [ "OP_G" , "SZ_W" ],
+ "Gv" : [ "OP_G" , "SZ_V" ],
+ "Gvw" : [ "OP_G" , "SZ_MDQ" ],
+ "Gd" : [ "OP_G" , "SZ_D" ],
+ "Gq" : [ "OP_G" , "SZ_Q" ],
+ "Gx" : [ "OP_G" , "SZ_MDQ" ],
+ "Gz" : [ "OP_G" , "SZ_Z" ],
+ "M" : [ "OP_M" , "SZ_NA" ],
+ "Mb" : [ "OP_M" , "SZ_B" ],
+ "Mw" : [ "OP_M" , "SZ_W" ],
+ "Ms" : [ "OP_M" , "SZ_W" ],
+ "Md" : [ "OP_M" , "SZ_D" ],
+ "Mq" : [ "OP_M" , "SZ_Q" ],
+ "Mt" : [ "OP_M" , "SZ_T" ],
+ "Mo" : [ "OP_M" , "SZ_O" ],
+ "I1" : [ "OP_I1" , "SZ_NA" ],
+ "I3" : [ "OP_I3" , "SZ_NA" ],
+ "Ib" : [ "OP_I" , "SZ_B" ],
+ "Isb" : [ "OP_I" , "SZ_SB" ],
+ "Iw" : [ "OP_I" , "SZ_W" ],
+ "Iv" : [ "OP_I" , "SZ_V" ],
+ "Iz" : [ "OP_I" , "SZ_Z" ],
+ "Jv" : [ "OP_J" , "SZ_V" ],
+ "Jz" : [ "OP_J" , "SZ_Z" ],
+ "Jb" : [ "OP_J" , "SZ_B" ],
+ "R" : [ "OP_R" , "SZ_RDQ" ],
+ "C" : [ "OP_C" , "SZ_NA" ],
+ "D" : [ "OP_D" , "SZ_NA" ],
+ "S" : [ "OP_S" , "SZ_NA" ],
+ "Ob" : [ "OP_O" , "SZ_B" ],
+ "Ow" : [ "OP_O" , "SZ_W" ],
+ "Ov" : [ "OP_O" , "SZ_V" ],
+ "V" : [ "OP_V" , "SZ_NA" ],
+ "W" : [ "OP_W" , "SZ_NA" ],
+ "P" : [ "OP_P" , "SZ_NA" ],
+ "Q" : [ "OP_Q" , "SZ_NA" ],
+ "VR" : [ "OP_VR" , "SZ_NA" ],
+ "PR" : [ "OP_PR" , "SZ_NA" ],
+ "AL" : [ "OP_AL" , "SZ_NA" ],
+ "CL" : [ "OP_CL" , "SZ_NA" ],
+ "DL" : [ "OP_DL" , "SZ_NA" ],
+ "BL" : [ "OP_BL" , "SZ_NA" ],
+ "AH" : [ "OP_AH" , "SZ_NA" ],
+ "CH" : [ "OP_CH" , "SZ_NA" ],
+ "DH" : [ "OP_DH" , "SZ_NA" ],
+ "BH" : [ "OP_BH" , "SZ_NA" ],
+ "AX" : [ "OP_AX" , "SZ_NA" ],
+ "CX" : [ "OP_CX" , "SZ_NA" ],
+ "DX" : [ "OP_DX" , "SZ_NA" ],
+ "BX" : [ "OP_BX" , "SZ_NA" ],
+ "SI" : [ "OP_SI" , "SZ_NA" ],
+ "DI" : [ "OP_DI" , "SZ_NA" ],
+ "SP" : [ "OP_SP" , "SZ_NA" ],
+ "BP" : [ "OP_BP" , "SZ_NA" ],
+ "eAX" : [ "OP_eAX" , "SZ_NA" ],
+ "eCX" : [ "OP_eCX" , "SZ_NA" ],
+ "eDX" : [ "OP_eDX" , "SZ_NA" ],
+ "eBX" : [ "OP_eBX" , "SZ_NA" ],
+ "eSI" : [ "OP_eSI" , "SZ_NA" ],
+ "eDI" : [ "OP_eDI" , "SZ_NA" ],
+ "eSP" : [ "OP_eSP" , "SZ_NA" ],
+ "eBP" : [ "OP_eBP" , "SZ_NA" ],
+ "rAX" : [ "OP_rAX" , "SZ_NA" ],
+ "rCX" : [ "OP_rCX" , "SZ_NA" ],
+ "rBX" : [ "OP_rBX" , "SZ_NA" ],
+ "rDX" : [ "OP_rDX" , "SZ_NA" ],
+ "rSI" : [ "OP_rSI" , "SZ_NA" ],
+ "rDI" : [ "OP_rDI" , "SZ_NA" ],
+ "rSP" : [ "OP_rSP" , "SZ_NA" ],
+ "rBP" : [ "OP_rBP" , "SZ_NA" ],
+ "ES" : [ "OP_ES" , "SZ_NA" ],
+ "CS" : [ "OP_CS" , "SZ_NA" ],
+ "DS" : [ "OP_DS" , "SZ_NA" ],
+ "SS" : [ "OP_SS" , "SZ_NA" ],
+ "GS" : [ "OP_GS" , "SZ_NA" ],
+ "FS" : [ "OP_FS" , "SZ_NA" ],
+ "ST0" : [ "OP_ST0" , "SZ_NA" ],
+ "ST1" : [ "OP_ST1" , "SZ_NA" ],
+ "ST2" : [ "OP_ST2" , "SZ_NA" ],
+ "ST3" : [ "OP_ST3" , "SZ_NA" ],
+ "ST4" : [ "OP_ST4" , "SZ_NA" ],
+ "ST5" : [ "OP_ST5" , "SZ_NA" ],
+ "ST6" : [ "OP_ST6" , "SZ_NA" ],
+ "ST7" : [ "OP_ST7" , "SZ_NA" ],
+ "NONE" : [ "OP_NONE" , "SZ_NA" ],
+ "ALr8b" : [ "OP_ALr8b" , "SZ_NA" ],
+ "CLr9b" : [ "OP_CLr9b" , "SZ_NA" ],
+ "DLr10b" : [ "OP_DLr10b" , "SZ_NA" ],
+ "BLr11b" : [ "OP_BLr11b" , "SZ_NA" ],
+ "AHr12b" : [ "OP_AHr12b" , "SZ_NA" ],
+ "CHr13b" : [ "OP_CHr13b" , "SZ_NA" ],
+ "DHr14b" : [ "OP_DHr14b" , "SZ_NA" ],
+ "BHr15b" : [ "OP_BHr15b" , "SZ_NA" ],
+ "rAXr8" : [ "OP_rAXr8" , "SZ_NA" ],
+ "rCXr9" : [ "OP_rCXr9" , "SZ_NA" ],
+ "rDXr10" : [ "OP_rDXr10" , "SZ_NA" ],
+ "rBXr11" : [ "OP_rBXr11" , "SZ_NA" ],
+ "rSPr12" : [ "OP_rSPr12" , "SZ_NA" ],
+ "rBPr13" : [ "OP_rBPr13" , "SZ_NA" ],
+ "rSIr14" : [ "OP_rSIr14" , "SZ_NA" ],
+ "rDIr15" : [ "OP_rDIr15" , "SZ_NA" ],
+ "jWP" : [ "OP_J" , "SZ_WP" ],
+ "jDP" : [ "OP_J" , "SZ_DP" ],
+
+}
+
+#
+# opcode prefix dictionary
+#
+pfx_dict = {
+ "aso" : "P_aso",
+ "oso" : "P_oso",
+ "rexw" : "P_rexw",
+ "rexb" : "P_rexb",
+ "rexx" : "P_rexx",
+ "rexr" : "P_rexr",
+ "inv64" : "P_inv64",
+ "def64" : "P_def64",
+ "depM" : "P_depM",
+ "cast1" : "P_c1",
+ "cast2" : "P_c2",
+ "cast3" : "P_c3"
+}
+
+
+#
+# globals
+#
+opr_constants = []
+siz_constants = []
+tables = {}
+table_sizes = {}
+mnm_list = []
+default_opr = 'O_NONE, O_NONE, O_NONE'
+
+
+#
+# collect the operand/size constants
+#
+for o in operand_dict.keys():
+ if not (operand_dict[o][0] in opr_constants):
+ opr_constants.append(operand_dict[o][0])
+ if not (operand_dict[o][1] in siz_constants):
+ siz_constants.append(operand_dict[o][1])
+
+xmlDoc = minidom.parse(sys.argv[1])
+tlNode = xmlDoc.firstChild
+
+#
+# look for top-level optable node
+#
+while tlNode and tlNode.localName != "x86optable": tlNode = tlNode.nextSibling
+
+#
+# creates a table entry
+#
+def centry(i, defmap):
+ if defmap["type"][0:3] == "grp":
+ opr = default_opr
+ mnm = 'UD_I' + defmap["type"].lower()
+ pfx = defmap["name"].upper()
+ elif defmap["type"] == "leaf":
+ mnm = "UD_I" + defmap["name"]
+ opr = defmap["opr"]
+ pfx = defmap["pfx"]
+ if len(mnm) == 0: mnm = "UD_Ina"
+ if len(opr) == 0: opr = default_opr
+ if len(pfx) == 0: pfx = "P_none"
+ else:
+ opr = default_opr
+ pfx = "P_none"
+ mnm = "UD_Iinvalid"
+
+ return " /* %s */ { %-16s %-26s %s },\n" % (i, mnm + ',', opr + ',', pfx)
+
+#
+# makes a new table and adds it to the global
+# list of tables
+#
+def mktab(name, size):
+ if not (name in tables.keys()):
+ tables[name] = {}
+ table_sizes[name] = size
+
+for node in tlNode.childNodes:
+
+ opcodes = []
+ iclass = ''
+ vendor = ''
+
+ # we are only interested in <instruction>
+ if node.localName != 'instruction':
+ continue
+
+ # we need the mnemonic attribute
+ if not ('mnemonic' in node.attributes.keys()):
+ print "error: no mnemonic given in <instruction>."
+ sys.exit(-1)
+
+ # check if this instruction was already defined.
+ # else add it to the global list of mnemonics
+ mnemonic = node.attributes['mnemonic'].value
+ if mnemonic in mnm_list:
+ print "error: multiple declarations of mnemonic='%s'" % mnemonic;
+ sys.exit(-1)
+ else:
+ mnm_list.append(mnemonic)
+
+ #
+ # collect instruction
+ # - vendor
+ # - class
+ #
+ for n in node.childNodes:
+ if n.localName == 'vendor':
+ vendor = (n.firstChild.data).strip();
+ elif n.localName == 'class':
+ iclass = n.firstChild.data;
+
+ #
+ # for each opcode definition
+ #
+ for n in node.childNodes:
+ if n.localName != 'opcode':
+ continue;
+
+ opcode = n.firstChild.data.strip();
+ parts = opcode.split(";");
+ flags = []
+ opr = []
+ pfx = []
+ opr = []
+ pfx_c = []
+
+ # get cast attribute, if given
+ if 'cast' in n.attributes.keys():
+ pfx_c.append( "P_c" + n.attributes['cast'].value )
+
+ # get implicit addressing attribute, if given
+ if 'imp_addr' in n.attributes.keys():
+ if int( n.attributes['imp_addr'].value ):
+ pfx_c.append( "P_ImpAddr" )
+
+ # get mode attribute, if given
+ if 'mode' in n.attributes.keys():
+ v = (n.attributes['mode'].value).strip()
+ modef = v.split();
+ for m in modef:
+ if not (m in pfx_dict):
+ print "warning: unrecognized mode attribute '%s'" % m
+ else:
+ pfx_c.append(pfx_dict[m])
+
+ #
+ # split opcode definition into
+ # 1. prefixes (pfx)
+ # 2. opcode bytes (opc)
+ # 3. operands
+ #
+ if len(parts) == 1:
+ opc = parts[0].split()
+ elif len(parts) == 2:
+ opc = parts[0].split()
+ opr = parts[1].split()
+ for o in opc:
+ if o in pfx_dict:
+ pfx = parts[0].split()
+ opc = parts[1].split()
+ break
+ elif len(parts) == 3:
+ pfx = parts[0].split()
+ opc = parts[1].split()
+ opr = parts[2].split()
+ else:
+ print "error: invalid opcode definition of %s\n" % mnemonic
+ sys.exit(-1)
+ # Convert opcodes to upper case
+ for i in range(len(opc)):
+ opc[i] = opc[i].upper()
+
+ #
+ # check for special cases of instruction translation
+ # and ignore them
+ #
+ if mnemonic == 'pause' or \
+ ( mnemonic == 'nop' and opc[0] == '90' ) or \
+ mnemonic == 'invalid' or \
+ mnemonic == 'db' :
+ continue
+
+ #
+ # Convert prefix
+ #
+ for p in pfx:
+ if not ( p in pfx_dict.keys() ):
+ print "error: invalid prefix specification: %s \n" % pfx
+ pfx_c.append( pfx_dict[p] )
+ if len(pfx) == 0:
+ pfx_c.append( "P_none" )
+ pfx = "|".join( pfx_c )
+
+ #
+ # Convert operands
+ #
+ opr_c = [ "O_NONE", "O_NONE", "O_NONE" ]
+ for i in range(len(opr)):
+ if not (opr[i] in operand_dict.keys()):
+ print "error: invalid operand declaration: %s\n" % opr[i]
+ opr_c[i] = "O_" + opr[i]
+ opr = "%-8s %-8s %s" % (opr_c[0] + ",", opr_c[1] + ",", opr_c[2])
+
+ table_sse = ''
+ table_name = 'itab__1byte'
+ table_size = 256
+ table_index = ''
+
+ for op in opc:
+ if op[0:3] == 'SSE':
+ table_sse = op
+ elif op == '0F' and len(table_sse):
+ table_name = "itab__pfx_%s__0f" % table_sse
+ table_size = 256
+ table_sse = ''
+ elif op == '0F':
+ table_name = "itab__0f"
+ table_size = 256
+ elif op == '38' and (table_name == "itab__0f" or
+ table_name == "itab__pfx_SSE66__0f"):
+ table_index = '38'
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_3byte', \
+ 'name' : "%s__38" % (table_name) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ table_size = 256
+ elif op[0:5] == '/X87=':
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_x87', \
+ 'name' : "%s__op_%s__x87" % (table_name, table_index) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ table_index = "%02X" % int(op[5:7], 16)
+ table_size = 64
+ elif op[0:4] == '/RM=':
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_rm', \
+ 'name' : "%s__op_%s__rm" % (table_name, table_index) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ table_index = "%02X" % int(op[4:6])
+ table_size = 8
+ elif op[0:5] == '/MOD=':
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_mod', \
+ 'name' : "%s__op_%s__mod" % (table_name, table_index) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ if len(op) == 8:
+ v = op[5:8]
+ else:
+ v = op[5:7]
+ mod_dict = { '!11' : 0, '11' : 1 }
+ table_index = "%02X" % int(mod_dict[v])
+ table_size = 2
+ elif op[0:2] == '/O':
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_osize', \
+ 'name' : "%s__op_%s__osize" % (table_name, table_index) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ table_index = "%02X" % int(mode_dict[op[2:4]])
+ table_size = 3
+ elif op[0:2] == '/A':
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_asize', \
+ 'name' : "%s__op_%s__asize" % (table_name, table_index) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ table_index = "%02X" % int(mode_dict[op[2:4]])
+ table_size = 3
+ elif op[0:2] == '/M':
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_mode', \
+ 'name' : "%s__op_%s__mode" % (table_name, table_index) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ table_index = "%02X" % int(mode_dict[op[2:4]])
+ table_size = 3
+ elif op[0:6] == '/3DNOW':
+ table_name = "itab__3dnow"
+ table_size = 256
+ elif op[0:1] == '/':
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_reg', \
+ 'name' : "%s__op_%s__reg" % (table_name, table_index) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ table_index = "%02X" % int(op[1:2])
+ table_size = 8
+ else:
+ table_index = op
+
+ mktab(table_name, table_size)
+
+ if len(vendor):
+ tables[table_name][table_index] = { \
+ 'type' : 'grp_vendor', \
+ 'name' : "%s__op_%s__vendor" % (table_name, table_index) \
+ }
+ table_name = tables[table_name][table_index]['name']
+ table_index = vend_dict[vendor]
+ table_size = 3
+ mktab(table_name, table_size)
+
+ tables[table_name][table_index] = { \
+ 'type' : 'leaf', \
+ 'name' : mnemonic, \
+ 'pfx' : pfx, \
+ 'opr' : opr, \
+ 'flags' : flags \
+ }
+
+ if len(vendor):
+ tables[table_name][vend_dict['ANY']] = { \
+ 'type' : 'leaf', \
+ 'name' : mnemonic, \
+ 'pfx' : pfx, \
+ 'opr' : opr, \
+ 'flags' : flags \
+ }
+
+# ---------------------------------------------------------------------
+# Generate itab.h
+# ---------------------------------------------------------------------
+
+f = open("itab.h", "w")
+
+f.write('''
+/* itab.h -- auto generated by opgen.py, do not edit. */
+
+#ifndef UD_ITAB_H
+#define UD_ITAB_H
+
+''')
+
+#
+# Generate enumeration of size constants
+#
+siz_constants.sort()
+f.write('''
+''')
+
+f.write("\nenum ud_itab_vendor_index {\n" )
+f.write(" ITAB__VENDOR_INDX__AMD,\n" )
+f.write(" ITAB__VENDOR_INDX__INTEL,\n" )
+f.write(" ITAB__VENDOR_INDX__ANY,\n" )
+f.write("};\n\n")
+
+
+f.write("\nenum ud_itab_mode_index {\n" )
+f.write(" ITAB__MODE_INDX__16,\n" )
+f.write(" ITAB__MODE_INDX__32,\n" )
+f.write(" ITAB__MODE_INDX__64\n" )
+f.write("};\n\n")
+
+
+f.write("\nenum ud_itab_mod_index {\n" )
+f.write(" ITAB__MOD_INDX__NOT_11,\n" )
+f.write(" ITAB__MOD_INDX__11\n" )
+f.write("};\n\n")
+
+#
+# Generate enumeration of the tables
+#
+table_names = tables.keys()
+table_names.sort();
+
+f.write( "\nenum ud_itab_index {\n" )
+for name in table_names:
+ f.write(" %s,\n" % name.upper() );
+f.write( "};\n\n" )
+
+#
+# Generate mnemonics list
+#
+f.write("\nenum __attribute__((packed)) ud_mnemonic_code {\n")
+for m in mnm_list:
+ f.write(" UD_I%s,\n" % m)
+for m in spl_mnm_types:
+ f.write(" UD_I%s,\n" % m)
+f.write("};\n\n")
+
+#
+# Generate operand definitions
+#
+f.write("\n/* itab entry operand definitions */\n\n");
+operands = operand_dict.keys()
+operands.sort()
+for o in operands:
+ f.write("#define O_%-7s { %-12s %-8s }\n" %
+ (o, operand_dict[o][0] + ",", operand_dict[o][1]));
+f.write("\n");
+
+#
+# Generate struct defs
+#
+f.write( \
+'''
+
+extern const char* ud_mnemonics_str[];;
+extern struct ud_itab_entry* ud_itab_list[];
+
+''' )
+
+
+f.write("#endif\n")
+
+f.close()
+
+# ---------------------------------------------------------------------
+# Generate itab.c
+# ---------------------------------------------------------------------
+
+f = open("itab.c", "w")
+
+f.write('''
+/* itab.c -- auto generated by opgen.py, do not edit. */
+
+#include "types.h"
+#include "decode.h"
+#include "itab.h"
+
+''')
+
+#
+# generate mnemonic list
+#
+f.write("const char * ud_mnemonics_str[] = {\n")
+for m in mnm_list:
+ f.write(" \"%s\",\n" % m )
+f.write("};\n\n")
+
+#
+# generate instruction tables
+#
+
+f.write("\n")
+for t in table_names:
+ f.write("\nstatic struct ud_itab_entry " + t.lower() + "[%d] = {\n" % table_sizes[t]);
+ for i in range(int(table_sizes[t])):
+ index = "%02X" % i
+ if index in tables[t]:
+ f.write(centry(index, tables[t][index]))
+ else:
+ f.write(centry(index,{"type":"invalid"}))
+ f.write("};\n");
+
+#
+# write the instruction table list
+#
+f.write( "\n/* the order of this table matches enum ud_itab_index */")
+f.write( "\nstruct ud_itab_entry * ud_itab_list[] = {\n" )
+for name in table_names:
+ f.write( " %s,\n" % name.lower() )
+f.write( "};\n" );
+
+f.close();
+
+# vim:expandtab
+# vim:sw=4
+# vim:ts=4
--- /dev/null
+/* udis86 - libudis86/syn-att.c
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "types.h"
+#include "extern.h"
+#include "decode.h"
+#include "itab.h"
+#include "syn.h"
+
+/* -----------------------------------------------------------------------------
+ * opr_cast() - Prints an operand cast.
+ * -----------------------------------------------------------------------------
+ */
+static void
+opr_cast(struct ud* u, struct ud_operand* op)
+{
+ switch(op->size) {
+ case 16 : case 32 :
+ mkasm(u, "*"); break;
+ default: break;
+ }
+}
+
+/* -----------------------------------------------------------------------------
+ * gen_operand() - Generates assembly output for each operand.
+ * -----------------------------------------------------------------------------
+ */
+static void
+gen_operand(struct ud* u, struct ud_operand* op)
+{
+ switch(op->type) {
+ case UD_OP_REG:
+ mkasm(u, "%%%s", ud_reg_tab[op->base - UD_R_AL]);
+ break;
+
+ case UD_OP_MEM:
+ if (u->br_far) opr_cast(u, op);
+ if (u->pfx_seg)
+ mkasm(u, "%%%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]);
+ if (op->offset == 8) {
+ if (op->lval.sbyte < 0)
+ mkasm(u, "-0x%x", (-op->lval.sbyte) & 0xff);
+ else mkasm(u, "0x%x", op->lval.sbyte);
+ }
+ else if (op->offset == 16)
+ mkasm(u, "0x%x", op->lval.uword);
+ else if (op->offset == 32)
+ mkasm(u, "0x%lx", op->lval.udword);
+ else if (op->offset == 64)
+ mkasm(u, "0x" FMT64 "x", op->lval.uqword);
+
+ if (op->base)
+ mkasm(u, "(%%%s", ud_reg_tab[op->base - UD_R_AL]);
+ if (op->index) {
+ if (op->base)
+ mkasm(u, ",");
+ else mkasm(u, "(");
+ mkasm(u, "%%%s", ud_reg_tab[op->index - UD_R_AL]);
+ }
+ if (op->scale)
+ mkasm(u, ",%d", op->scale);
+ if (op->base || op->index)
+ mkasm(u, ")");
+ break;
+
+ case UD_OP_IMM:
+ switch (op->size) {
+ case 8: mkasm(u, "$0x%x", op->lval.ubyte); break;
+ case 16: mkasm(u, "$0x%x", op->lval.uword); break;
+ case 32: mkasm(u, "$0x%lx", op->lval.udword); break;
+ case 64: mkasm(u, "$0x" FMT64 "x", op->lval.uqword); break;
+ default: break;
+ }
+ break;
+
+ case UD_OP_JIMM:
+ switch (op->size) {
+ case 8:
+ mkasm(u, "0x" FMT64 "x", u->pc + op->lval.sbyte);
+ break;
+ case 16:
+ mkasm(u, "0x" FMT64 "x", u->pc + op->lval.sword);
+ break;
+ case 32:
+ mkasm(u, "0x" FMT64 "x", u->pc + op->lval.sdword);
+ break;
+ default:break;
+ }
+ break;
+
+ case UD_OP_PTR:
+ switch (op->size) {
+ case 32:
+ mkasm(u, "$0x%x, $0x%x", op->lval.ptr.seg,
+ op->lval.ptr.off & 0xFFFF);
+ break;
+ case 48:
+ mkasm(u, "$0x%x, $0x%lx", op->lval.ptr.seg,
+ op->lval.ptr.off);
+ break;
+ }
+ break;
+
+ default: return;
+ }
+}
+
+/* =============================================================================
+ * translates to AT&T syntax
+ * =============================================================================
+ */
+extern void
+ud_translate_att(struct ud *u)
+{
+ int size = 0;
+
+ /* check if P_OSO prefix is used */
+ if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) {
+ switch (u->dis_mode) {
+ case 16:
+ mkasm(u, "o32 ");
+ break;
+ case 32:
+ case 64:
+ mkasm(u, "o16 ");
+ break;
+ }
+ }
+
+ /* check if P_ASO prefix was used */
+ if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) {
+ switch (u->dis_mode) {
+ case 16:
+ mkasm(u, "a32 ");
+ break;
+ case 32:
+ mkasm(u, "a16 ");
+ break;
+ case 64:
+ mkasm(u, "a32 ");
+ break;
+ }
+ }
+
+ if (u->pfx_lock)
+ mkasm(u, "lock ");
+ if (u->pfx_rep)
+ mkasm(u, "rep ");
+ if (u->pfx_repne)
+ mkasm(u, "repne ");
+
+ /* special instructions */
+ switch (u->mnemonic) {
+ case UD_Iretf:
+ mkasm(u, "lret ");
+ break;
+ case UD_Idb:
+ mkasm(u, ".byte 0x%x", u->operand[0].lval.ubyte);
+ return;
+ case UD_Ijmp:
+ case UD_Icall:
+ if (u->br_far) mkasm(u, "l");
+ mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic));
+ break;
+ case UD_Ibound:
+ case UD_Ienter:
+ if (u->operand[0].type != UD_NONE)
+ gen_operand(u, &u->operand[0]);
+ if (u->operand[1].type != UD_NONE) {
+ mkasm(u, ",");
+ gen_operand(u, &u->operand[1]);
+ }
+ return;
+ default:
+ mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic));
+ }
+
+ if (u->c1)
+ size = u->operand[0].size;
+ else if (u->c2)
+ size = u->operand[1].size;
+ else if (u->c3)
+ size = u->operand[2].size;
+
+ if (size == 8)
+ mkasm(u, "b");
+ else if (size == 16)
+ mkasm(u, "w");
+ else if (size == 64)
+ mkasm(u, "q");
+
+ mkasm(u, " ");
+
+ if (u->operand[2].type != UD_NONE) {
+ gen_operand(u, &u->operand[2]);
+ mkasm(u, ", ");
+ }
+
+ if (u->operand[1].type != UD_NONE) {
+ gen_operand(u, &u->operand[1]);
+ mkasm(u, ", ");
+ }
+
+ if (u->operand[0].type != UD_NONE)
+ gen_operand(u, &u->operand[0]);
+}
--- /dev/null
+/* udis86 - libudis86/syn-intel.c
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "types.h"
+#include "extern.h"
+#include "decode.h"
+#include "itab.h"
+#include "syn.h"
+
+/* -----------------------------------------------------------------------------
+ * opr_cast() - Prints an operand cast.
+ * -----------------------------------------------------------------------------
+ */
+static void
+opr_cast(struct ud* u, struct ud_operand* op)
+{
+ switch(op->size) {
+ case 8: mkasm(u, "byte " ); break;
+ case 16: mkasm(u, "word " ); break;
+ case 32: mkasm(u, "dword "); break;
+ case 64: mkasm(u, "qword "); break;
+ case 80: mkasm(u, "tword "); break;
+ default: break;
+ }
+ if (u->br_far)
+ mkasm(u, "far ");
+ else if (u->br_near)
+ mkasm(u, "near ");
+}
+
+/* -----------------------------------------------------------------------------
+ * gen_operand() - Generates assembly output for each operand.
+ * -----------------------------------------------------------------------------
+ */
+static void gen_operand(struct ud* u, struct ud_operand* op, int syn_cast)
+{
+ switch(op->type) {
+ case UD_OP_REG:
+ mkasm(u, ud_reg_tab[op->base - UD_R_AL]);
+ break;
+
+ case UD_OP_MEM: {
+
+ int op_f = 0;
+
+ if (syn_cast)
+ opr_cast(u, op);
+
+ mkasm(u, "[");
+
+ if (u->pfx_seg)
+ mkasm(u, "%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]);
+
+ if (op->base) {
+ mkasm(u, "%s", ud_reg_tab[op->base - UD_R_AL]);
+ op_f = 1;
+ }
+
+ if (op->index) {
+ if (op_f)
+ mkasm(u, "+");
+ mkasm(u, "%s", ud_reg_tab[op->index - UD_R_AL]);
+ op_f = 1;
+ }
+
+ if (op->scale)
+ mkasm(u, "*%d", op->scale);
+
+ if (op->offset == 8) {
+ if (op->lval.sbyte < 0)
+ mkasm(u, "-0x%x", -op->lval.sbyte);
+ else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sbyte);
+ }
+ else if (op->offset == 16)
+ mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.uword);
+ else if (op->offset == 32) {
+ if (u->adr_mode == 64) {
+ if (op->lval.sdword < 0)
+ mkasm(u, "-0x%x", -op->lval.sdword);
+ else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sdword);
+ }
+ else mkasm(u, "%s0x%lx", (op_f) ? "+" : "", op->lval.udword);
+ }
+ else if (op->offset == 64)
+ mkasm(u, "%s0x" FMT64 "x", (op_f) ? "+" : "", op->lval.uqword);
+
+ mkasm(u, "]");
+ break;
+ }
+
+ case UD_OP_IMM:
+ if (syn_cast) opr_cast(u, op);
+ switch (op->size) {
+ case 8: mkasm(u, "0x%x", op->lval.ubyte); break;
+ case 16: mkasm(u, "0x%x", op->lval.uword); break;
+ case 32: mkasm(u, "0x%lx", op->lval.udword); break;
+ case 64: mkasm(u, "0x" FMT64 "x", op->lval.uqword); break;
+ default: break;
+ }
+ break;
+
+ case UD_OP_JIMM:
+ if (syn_cast) opr_cast(u, op);
+ switch (op->size) {
+ case 8:
+ mkasm(u, "0x" FMT64 "x", u->pc + op->lval.sbyte);
+ break;
+ case 16:
+ mkasm(u, "0x" FMT64 "x", u->pc + op->lval.sword);
+ break;
+ case 32:
+ mkasm(u, "0x" FMT64 "x", u->pc + op->lval.sdword);
+ break;
+ default:break;
+ }
+ break;
+
+ case UD_OP_PTR:
+ switch (op->size) {
+ case 32:
+ mkasm(u, "word 0x%x:0x%x", op->lval.ptr.seg,
+ op->lval.ptr.off & 0xFFFF);
+ break;
+ case 48:
+ mkasm(u, "dword 0x%x:0x%lx", op->lval.ptr.seg,
+ op->lval.ptr.off);
+ break;
+ }
+ break;
+
+ case UD_OP_CONST:
+ if (syn_cast) opr_cast(u, op);
+ mkasm(u, "%d", op->lval.udword);
+ break;
+
+ default: return;
+ }
+}
+
+/* =============================================================================
+ * translates to intel syntax
+ * =============================================================================
+ */
+extern void ud_translate_intel(struct ud* u)
+{
+ /* -- prefixes -- */
+
+ /* check if P_OSO prefix is used */
+ if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) {
+ switch (u->dis_mode) {
+ case 16:
+ mkasm(u, "o32 ");
+ break;
+ case 32:
+ case 64:
+ mkasm(u, "o16 ");
+ break;
+ }
+ }
+
+ /* check if P_ASO prefix was used */
+ if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) {
+ switch (u->dis_mode) {
+ case 16:
+ mkasm(u, "a32 ");
+ break;
+ case 32:
+ mkasm(u, "a16 ");
+ break;
+ case 64:
+ mkasm(u, "a32 ");
+ break;
+ }
+ }
+
+ if (u->pfx_lock)
+ mkasm(u, "lock ");
+ if (u->pfx_rep)
+ mkasm(u, "rep ");
+ if (u->pfx_repne)
+ mkasm(u, "repne ");
+ if (u->implicit_addr && u->pfx_seg)
+ mkasm(u, "%s ", ud_reg_tab[u->pfx_seg - UD_R_AL]);
+
+ /* print the instruction mnemonic */
+ mkasm(u, "%s ", ud_lookup_mnemonic(u->mnemonic));
+
+ /* operand 1 */
+ if (u->operand[0].type != UD_NONE) {
+ gen_operand(u, &u->operand[0], u->c1);
+ }
+ /* operand 2 */
+ if (u->operand[1].type != UD_NONE) {
+ mkasm(u, ", ");
+ gen_operand(u, &u->operand[1], u->c2);
+ }
+
+ /* operand 3 */
+ if (u->operand[2].type != UD_NONE) {
+ mkasm(u, ", ");
+ gen_operand(u, &u->operand[2], u->c3);
+ }
+}
--- /dev/null
+/* udis86 - libudis86/syn.c
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* -----------------------------------------------------------------------------
+ * Intel Register Table - Order Matters (types.h)!
+ * -----------------------------------------------------------------------------
+ */
+const char* ud_reg_tab[] =
+{
+ "al", "cl", "dl", "bl",
+ "ah", "ch", "dh", "bh",
+ "spl", "bpl", "sil", "dil",
+ "r8b", "r9b", "r10b", "r11b",
+ "r12b", "r13b", "r14b", "r15b",
+
+ "ax", "cx", "dx", "bx",
+ "sp", "bp", "si", "di",
+ "r8w", "r9w", "r10w", "r11w",
+ "r12w", "r13W" , "r14w", "r15w",
+
+ "eax", "ecx", "edx", "ebx",
+ "esp", "ebp", "esi", "edi",
+ "r8d", "r9d", "r10d", "r11d",
+ "r12d", "r13d", "r14d", "r15d",
+
+ "rax", "rcx", "rdx", "rbx",
+ "rsp", "rbp", "rsi", "rdi",
+ "r8", "r9", "r10", "r11",
+ "r12", "r13", "r14", "r15",
+
+ "es", "cs", "ss", "ds",
+ "fs", "gs",
+
+ "cr0", "cr1", "cr2", "cr3",
+ "cr4", "cr5", "cr6", "cr7",
+ "cr8", "cr9", "cr10", "cr11",
+ "cr12", "cr13", "cr14", "cr15",
+
+ "dr0", "dr1", "dr2", "dr3",
+ "dr4", "dr5", "dr6", "dr7",
+ "dr8", "dr9", "dr10", "dr11",
+ "dr12", "dr13", "dr14", "dr15",
+
+ "mm0", "mm1", "mm2", "mm3",
+ "mm4", "mm5", "mm6", "mm7",
+
+ "st0", "st1", "st2", "st3",
+ "st4", "st5", "st6", "st7",
+
+ "xmm0", "xmm1", "xmm2", "xmm3",
+ "xmm4", "xmm5", "xmm6", "xmm7",
+ "xmm8", "xmm9", "xmm10", "xmm11",
+ "xmm12", "xmm13", "xmm14", "xmm15",
+
+ "rip"
+};
--- /dev/null
+/* udis86 - libudis86/syn.h
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/* -----------------------------------------------------------------------------
+ * syn.h
+ *
+ * Copyright (c) 2006, Vivek Mohan <vivek@sig9.com>
+ * All rights reserved. See LICENSE
+ * -----------------------------------------------------------------------------
+ */
+#ifndef UD_SYN_H
+#define UD_SYN_H
+
+#include "types.h"
+#ifndef __UD_STANDALONE__
+# include <stdarg.h>
+#endif /* __UD_STANDALONE__ */
+
+extern const char* ud_reg_tab[];
+
+static void mkasm(struct ud* u, const char* fmt, ...)
+{
+ va_list ap;
+ va_start(ap, fmt);
+ u->insn_fill += vsprintf((char*) u->insn_buffer + u->insn_fill, fmt, ap);
+ va_end(ap);
+}
+
+#endif
--- /dev/null
+/* udis86 - libudis86/types.h
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef UD_TYPES_H
+#define UD_TYPES_H
+
+#ifdef __KERNEL__
+ /* -D__KERNEL__ is automatically passed on the command line when
+ building something as part of the Linux kernel */
+# include <linux/kernel.h>
+# include <linux/string.h>
+# define __UD_STANDALONE__ 1
+#endif /* __KERNEL__ */
+
+#include "itab.h"
+
+#ifndef __UD_STANDALONE__
+# include <stdio.h>
+#endif /* __UD_STANDALONE__ */
+
+#ifdef _MSC_VER
+# define FMT64 "%I64"
+ typedef unsigned __int8 uint8_t;
+ typedef unsigned __int16 uint16_t;
+ typedef unsigned __int32 uint32_t;
+ typedef unsigned __int64 uint64_t;
+ typedef __int8 int8_t;
+ typedef __int16 int16_t;
+ typedef __int32 int32_t;
+ typedef __int64 int64_t;
+#else
+# define FMT64 "%ll"
+# ifndef __UD_STANDALONE__
+# include <inttypes.h>
+# endif /* __UD_STANDALONE__ */
+#endif
+
+/* -----------------------------------------------------------------------------
+ * All possible "types" of objects in udis86. Order is Important!
+ * -----------------------------------------------------------------------------
+ */
+enum ud_type
+{
+ UD_NONE,
+
+ /* 8 bit GPRs */
+ UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL,
+ UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH,
+ UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL,
+ UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B,
+ UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B,
+
+ /* 16 bit GPRs */
+ UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX,
+ UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI,
+ UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W,
+ UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W,
+
+ /* 32 bit GPRs */
+ UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX,
+ UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI,
+ UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D,
+ UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D,
+
+ /* 64 bit GPRs */
+ UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX,
+ UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI,
+ UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11,
+ UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15,
+
+ /* segment registers */
+ UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS,
+ UD_R_FS, UD_R_GS,
+
+ /* control registers*/
+ UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3,
+ UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7,
+ UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11,
+ UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15,
+
+ /* debug registers */
+ UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3,
+ UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7,
+ UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11,
+ UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15,
+
+ /* mmx registers */
+ UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3,
+ UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7,
+
+ /* x87 registers */
+ UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3,
+ UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7,
+
+ /* extended multimedia registers */
+ UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3,
+ UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7,
+ UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11,
+ UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15,
+
+ UD_R_RIP,
+
+ /* Operand Types */
+ UD_OP_REG, UD_OP_MEM, UD_OP_PTR, UD_OP_IMM,
+ UD_OP_JIMM, UD_OP_CONST
+};
+
+/* -----------------------------------------------------------------------------
+ * struct ud_operand - Disassembled instruction Operand.
+ * -----------------------------------------------------------------------------
+ */
+struct ud_operand
+{
+ enum ud_type type;
+ uint8_t size;
+ union {
+ int8_t sbyte;
+ uint8_t ubyte;
+ int16_t sword;
+ uint16_t uword;
+ int32_t sdword;
+ uint32_t udword;
+ int64_t sqword;
+ uint64_t uqword;
+
+ struct {
+ uint16_t seg;
+ uint32_t off;
+ } ptr;
+ } lval;
+
+ enum ud_type base;
+ enum ud_type index;
+ uint8_t offset;
+ uint8_t scale;
+};
+
+/* -----------------------------------------------------------------------------
+ * struct ud - The udis86 object.
+ * -----------------------------------------------------------------------------
+ */
+struct ud
+{
+ int (*inp_hook) (struct ud*);
+ uint8_t inp_curr;
+ uint8_t inp_fill;
+#ifndef __UD_STANDALONE__
+ FILE* inp_file;
+#endif
+ uint8_t inp_ctr;
+ uint8_t* inp_buff;
+ uint8_t* inp_buff_end;
+ uint8_t inp_end;
+ void (*translator)(struct ud*);
+ uint64_t insn_offset;
+ char insn_hexcode[32];
+ char insn_buffer[64];
+ unsigned int insn_fill;
+ uint8_t dis_mode;
+ uint64_t pc;
+ uint8_t vendor;
+ struct map_entry* mapen;
+ enum ud_mnemonic_code mnemonic;
+ struct ud_operand operand[3];
+ uint8_t error;
+ uint8_t pfx_rex;
+ uint8_t pfx_seg;
+ uint8_t pfx_opr;
+ uint8_t pfx_adr;
+ uint8_t pfx_lock;
+ uint8_t pfx_rep;
+ uint8_t pfx_repe;
+ uint8_t pfx_repne;
+ uint8_t pfx_insn;
+ uint8_t default64;
+ uint8_t opr_mode;
+ uint8_t adr_mode;
+ uint8_t br_far;
+ uint8_t br_near;
+ uint8_t implicit_addr;
+ uint8_t c1;
+ uint8_t c2;
+ uint8_t c3;
+ uint8_t inp_cache[256];
+ uint8_t inp_sess[64];
+ void * user_opaque_data;
+ struct ud_itab_entry * itab_entry;
+};
+
+/* -----------------------------------------------------------------------------
+ * Type-definitions
+ * -----------------------------------------------------------------------------
+ */
+typedef enum ud_type ud_type_t;
+typedef enum ud_mnemonic_code ud_mnemonic_code_t;
+
+typedef struct ud ud_t;
+typedef struct ud_operand ud_operand_t;
+
+#define UD_SYN_INTEL ud_translate_intel
+#define UD_SYN_ATT ud_translate_att
+#define UD_EOI -1
+#define UD_INP_CACHE_SZ 32
+#define UD_VENDOR_AMD 0
+#define UD_VENDOR_INTEL 1
+#define UD_VENDOR_ANY 2
+
+#define bail_out(ud,error_code) longjmp( (ud)->bailout, error_code )
+#define try_decode(ud) if ( setjmp( (ud)->bailout ) == 0 )
+#define catch_error() else
+
+#endif
--- /dev/null
+/* udis86 - libudis86/udis86.c
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __UD_STANDALONE__
+#include <stdlib.h>
+#include <string.h>
+#endif /* __UD_STANDALONE__ */
+
+#include "input.h"
+#include "extern.h"
+
+/* =============================================================================
+ * ud_init() - Initializes ud_t object.
+ * =============================================================================
+ */
+extern void
+ud_init(struct ud* u)
+{
+ memset((void*)u, 0, sizeof(struct ud));
+ ud_set_mode(u, 16);
+ u->mnemonic = UD_Iinvalid;
+ ud_set_pc(u, 0);
+#ifndef __UD_STANDALONE__
+ ud_set_input_file(u, stdin);
+#endif /* __UD_STANDALONE__ */
+}
+
+/* =============================================================================
+ * ud_disassemble() - disassembles one instruction and returns the number of
+ * bytes disassembled. A zero means end of disassembly.
+ * =============================================================================
+ */
+extern unsigned int
+ud_disassemble(struct ud* u)
+{
+ if (ud_input_end(u))
+ return 0;
+
+
+ u->insn_buffer[0] = u->insn_hexcode[0] = 0;
+
+
+ if (ud_decode(u) == 0)
+ return 0;
+ if (u->translator)
+ u->translator(u);
+ return ud_insn_len(u);
+}
+
+/* =============================================================================
+ * ud_set_mode() - Set Disassemly Mode.
+ * =============================================================================
+ */
+extern void
+ud_set_mode(struct ud* u, uint8_t m)
+{
+ switch(m) {
+ case 16:
+ case 32:
+ case 64: u->dis_mode = m ; return;
+ default: u->dis_mode = 16; return;
+ }
+}
+
+/* =============================================================================
+ * ud_set_vendor() - Set vendor.
+ * =============================================================================
+ */
+extern void
+ud_set_vendor(struct ud* u, unsigned v)
+{
+ switch(v) {
+ case UD_VENDOR_INTEL:
+ u->vendor = v;
+ break;
+ case UD_VENDOR_ANY:
+ u->vendor = v;
+ break;
+ default:
+ u->vendor = UD_VENDOR_AMD;
+ }
+}
+
+/* =============================================================================
+ * ud_set_pc() - Sets code origin.
+ * =============================================================================
+ */
+extern void
+ud_set_pc(struct ud* u, uint64_t o)
+{
+ u->pc = o;
+}
+
+/* =============================================================================
+ * ud_set_syntax() - Sets the output syntax.
+ * =============================================================================
+ */
+extern void
+ud_set_syntax(struct ud* u, void (*t)(struct ud*))
+{
+ u->translator = t;
+}
+
+/* =============================================================================
+ * ud_insn() - returns the disassembled instruction
+ * =============================================================================
+ */
+extern char*
+ud_insn_asm(struct ud* u)
+{
+ return u->insn_buffer;
+}
+
+/* =============================================================================
+ * ud_insn_offset() - Returns the offset.
+ * =============================================================================
+ */
+extern uint64_t
+ud_insn_off(struct ud* u)
+{
+ return u->insn_offset;
+}
+
+
+/* =============================================================================
+ * ud_insn_hex() - Returns hex form of disassembled instruction.
+ * =============================================================================
+ */
+extern char*
+ud_insn_hex(struct ud* u)
+{
+ return u->insn_hexcode;
+}
+
+/* =============================================================================
+ * ud_insn_ptr() - Returns code disassembled.
+ * =============================================================================
+ */
+extern uint8_t*
+ud_insn_ptr(struct ud* u)
+{
+ return u->inp_sess;
+}
+
+/* =============================================================================
+ * ud_insn_len() - Returns the count of bytes disassembled.
+ * =============================================================================
+ */
+extern unsigned int
+ud_insn_len(struct ud* u)
+{
+ return u->inp_ctr;
+}
--- /dev/null
+#
+# Automake definitions for ud/tests
+#
+check_PROGRAMS = gen ovrrun
+
+gen_SOURCES = gen.c
+gen_LDADD = ../libudis86/libudis86.la
+gen_CFLAGS = -I$(top_srcdir)/libudis86 -I$(top_srcdir)
+ovrrun_SOURCES = bufovrrun.c
+ovrrun_LDADD = ../libudis86/libudis86.la
+ovrrun_CFLAGS = -I$(top_srcdir)/libudis86 -I$(top_srcdir)
+
+YASM = yasm
+
+dist_check_DATA = test16.asm test32.asm test64.asm testjmp.asm testobscure.asm \
+ testjmp.ref testobscure.ref randtest.raw randtest16.ref \
+ randtest32.ref randtest64.ref
+
+check-local: tests
+
+tests: test16 test32 test64 testjmp bufovrrun randraw
+
+test16: gen
+ $(YASM) -f bin -o test16.bin $(top_srcdir)/tests/test16.asm
+ echo "[bits 16]" > test16.out
+ ./gen -16 < test16.bin >> test16.out
+ diff $(top_srcdir)/tests/test16.asm test16.out
+
+test32: gen
+ $(YASM) -f bin -o test32.bin $(top_srcdir)/tests/test32.asm
+ echo "[bits 32]" > test32.out
+ ./gen -32 < test32.bin >> test32.out
+ diff $(top_srcdir)/tests/test32.asm test32.out
+
+test64: gen
+ $(YASM) -f bin -o test64.bin $(top_srcdir)/tests/test64.asm
+ echo "[bits 64]" > test64.out
+ ./gen -64 < test64.bin >> test64.out
+ diff $(top_srcdir)/tests/test64.asm test64.out
+
+testjmp: gen
+ $(YASM) -f bin -o testjmp.bin $(top_srcdir)/tests/testjmp.asm
+ ../udcli/udcli -64 < testjmp.bin > testjmp.out
+ diff $(top_srcdir)/tests/testjmp.ref testjmp.out
+
+testobscure: gen
+ $(YASM) -f bin -o testobscure.bin $(top_srcdir)/tests/testobscure.asm
+ ./gen -32 < testobscure.bin > testobscure.out
+ diff $(top_srcdir)/tests/testobscure.ref testobscure.out
+
+bufovrrun: ovrrun
+ ./ovrrun
+
+randraw:
+ ./gen -16 < $(top_srcdir)/tests/randtest.raw > randtest16.out
+ diff randtest16.out $(top_srcdir)/tests/randtest16.ref
+ ./gen -32 < $(top_srcdir)/tests/randtest.raw > randtest32.out
+ diff randtest32.out $(top_srcdir)/tests/randtest32.ref
+ ./gen -64 < $(top_srcdir)/tests/randtest.raw > randtest64.out
+ diff randtest64.out $(top_srcdir)/tests/randtest64.ref
+
+installcheck-local:
+ $(CC) $(srcdir)/gen.c -o gen_installcheck.bin -I$(includedir) -L$(libdir) -ludis86
+
+clean-local:
+ rm -f *.bin *.out
--- /dev/null
+# Makefile
+
+CC = cl
+RM = del
+
+
+.SUFFIXES: .c .obj
+.c.obj:
+ $(CC) -I.. -c $(CFLAGS) -o $@ $<
+
+OBJS = gen.obj
+
+gen.exe: $(OBJS)
+ $(CC) $(OBJS) ../libudis86/udis86.lib -o gen.exe
+test16: gen.exe
+ yasm -f bin -o test16.bin test16.asm
+ echo [bits 16]> test16.out
+ gen -16 < test16.bin >> test16.out
+ diff test16.asm test16.out | more
+test32: gen.exe
+ yasm -f bin -o test32.bin test32.asm
+ echo [bits 32]> test32.out
+ gen -32 < test32.bin >> test32.out
+ diff test32.asm test32.out | more
+test64: gen.exe
+ yasm -f bin -o test64.bin test64.asm
+ echo [bits 64]> test64.out
+ gen -64 < test64.bin >> test64.out
+ diff test64.asm test64.out | more
+testjmp: gen.exe
+ yasm -f bin -o testjmp.bin testjmp.asm
+ ..\udcli\udcli -64 < testjmp.bin > testjmp.out
+ type testjmp.out | more
+clean:
+ $(RM) *.obj gen.exe *.bin *.out
--- /dev/null
+#include <stdio.h>
+#include <udis86.h>
+
+int
+main() {
+ uint8_t raw[] = { 0xf0, 0x66, 0x36, 0x67, 0x65, 0x66, 0xf3, 0x67, 0xda };
+ uint8_t len = 9;
+ ud_t ud_obj;
+ ud_init(&ud_obj);
+ ud_set_mode(&ud_obj, 16);
+ ud_set_input_buffer(&ud_obj, raw, len);
+ ud_set_syntax(&ud_obj, UD_SYN_INTEL);
+ if (ud_disassemble(&ud_obj) != 0) {
+ return 0;
+ }
+ return 1;
+}
--- /dev/null
+/* -----------------------------------------------------------------------------
+ * gen.c - front end to udis86 testing.
+ *
+ * Copyright (c) 2006,2007 Vivek Mohan <vivek@sig9.com>
+ * All rights reserved.
+ * See (LICENSE)
+ * -----------------------------------------------------------------------------
+ */
+#include <stdio.h>
+#include <string.h>
+#include <udis86.h>
+
+#if defined(__DJGPP__) || defined(_WIN32)
+# include <io.h>
+# include <fcntl.h>
+#endif
+
+#ifdef __DJGPP__
+# include <unistd.h> /* for isatty() */
+# define _setmode setmode
+# define _fileno fileno
+# define _O_BINARY O_BINARY
+#endif
+
+/* help string */
+int main(int argc, char **argv)
+{
+ ud_t ud_obj;
+
+#ifdef __DJGPP__
+ if ( !isatty( fileno( stdin ) ) )
+#endif
+#if defined(__DJGPP) || defined(_WIN32)
+ _setmode(_fileno(stdin), _O_BINARY);
+#endif
+
+ ud_init(&ud_obj);
+ ud_set_input_file(&ud_obj, stdin);
+
+ if (strcmp(argv[1],"-16") == 0)
+ ud_set_mode(&ud_obj, 16);
+ else if (strcmp(argv[1],"-32") == 0)
+ ud_set_mode(&ud_obj, 32);
+ else if (strcmp(argv[1],"-64") == 0)
+ ud_set_mode(&ud_obj, 64);
+
+ ud_set_syntax(&ud_obj, UD_SYN_INTEL);
+
+ while ( ud_disassemble( &ud_obj ) ) {
+ printf( "\t%s\n", ud_insn_asm( &ud_obj ) );
+ }
+
+ return 0;
+}
--- /dev/null
+ mov di, 0x4fae
+ adc byte [di+0xfaf1], 0x43
+ lea ax, [bx+si]
+ or al, 0xeb
+ aaa
+ add ax, 0x3a9d
+ retf 0x35cf
+ xor ax, 0xa132
+ cld
+ add word [gs:bx+si], 0xf8
+ out dx, ax
+ jmp word 0x7863:0x6e11
+ ret 0x6e60
+ mov cr1, [bx+di-0x6e]
+ jnp 0xffffffffffffffac
+ xchg si, ax
+ push es
+ lahf
+ add bl, ch
+ out 0x9f, al
+ sar word [bx+di-0x61], 1
+ jmp word 0x85e3:0x3f60
+ pusha
+ lock jl 0x81
+ mov cx, 0x2522
+ rol ax, cl
+ out 0x70, ax
+ push si
+ pop ss
+ aaa
+ in al, dx
+ xchg cx, ax
+ and bp, si
+ push cx
+ mov cl, 0xc8
+ sbb al, 0x78
+ into
+ shr bp, 1
+ adc bh, [si+0x21]
+ jnp 0xffffffffffffffe6
+ inc ax
+ push word [bp+si-0x1d]
+ xlatb
+ bound ax, [bp+di+0xd184]
+ neg word [bx+di+0x6df4]
+ xchg di, ax
+ mov gs, [0x8e1]
+ mov al, 0x96
+ adc [bp+di+0x585e], ah
+ insb
+ xchg dx, ax
+ ret 0x7e85
+ add ch, ch
+ pop ss
+ daa
+ xchg si, ax
+ mov bl, 0xe4
+ mov cr0, [bx+di+0x1807]
+ scasw
+ std
+ inc byte [si]
+ stosw
+ sbb word [si], 0x444e
+ outsw
+ mov [si+0x572e], bl
+ mov cx, 0xa448
+ or sp, dx
+ adc al, 0xe9
+ insw
+ sub cl, bl
+ invalid
+ cmc
+ bound ax, [bx+si]
+ pop ds
+ pop cx
+ mov [bx], ch
+ xchg dx, ax
+ salc
+ and [bx+di], sp
+ push bx
+ jbe 0xde
+ mov [bx+di], di
+ sar cl, cl
+ add [bp+di+0x5e], cl
+ inc bp
+ iretw
+ daa
+ mov gs, [bp+si]
+ adc ax, 0xe2e1
+ pop es
+ adc [bx+si+0x4b], dx
+ repne gs movsb
+ scasb
+ a32 inc sp
+ jae 0x130
+ ret
+ cmp ax, 0x1475
+ loope 0x128
+ stosw
+ insw
+ xor [si+0x98a4], si
+ add al, bh
+ imul si, [bp+di], 0xccc5
+ push 0xc8
+ cmp si, [bx+0x2958]
+ ret
+ wait
+ daa
+ xor al, [bx+si+0xc8bf]
+ push cx
+ mov ax, [0xe8a3]
+ mov al, [0x705f]
+ in ax, dx
+ add si, bx
+ xchg bx, ax
+ xor byte [bx+di+0x4f], 0x37
+ ja 0xa6
+ xlatb
+ o32 shl [bx+si], cl
+ mov bh, 0x91
+ push bp
+ push si
+ nop
+ push sp
+ mov bl, 0x83
+ invalid
+ pop cx
+ mov bx, 0xc4e3
+ pop ax
+ iretw
+ mov cx, [bx+si+0x20]
+ jbe 0x145
+ dec ebp
+ js 0x94
+ xor ch, [bx+si-0x65]
+ sahf
+ dec cx
+ or bh, [bp+0xdd9a]
+ ret 0x25db
+ invalid
+ xor al, 0x81
+ xchg [bp+si], bh
+ mov al, 0xd0
+ xchg sp, ax
+ push ss
+ sub ax, 0x27a4
+ sti
+ out 0xf5, ax
+ and ax, 0x47f6
+ pop di
+ jg 0x1a4
+ and word [fs:bp-0x79], 0xc980
+ rol byte [si+0x6699], 1
+ div word [bx-0x44]
+ sub bl, ch
+ push sp
+ or [bx+di+0x9a4a], dl
+ shr word [di+0x9f7b], cl
+ movsw
+ sub al, 0xe0
+ wait
+ push ss
+ invalid
+ test al, 0x7b
+ int3
+ cmpsw
+ in al, 0xac
+ mov dl, 0xd8
+ push sp
+ add di, cx
+ salc
+ push ss
+ bswap bp
+ sbb ax, 0x63c4
+ and al, 0x13
+ sub [bx+di+0xa3f5], al
+ mov ah, 0x98
+ fstp8 st1
+ or al, 0x40
+ out dx, ax
+ or [bx+di-0x47], sp
+ jae 0x162
+ call 0xffffffffffff8331
+ test [di+0xa6fe], dx
+ ficom dword [bx+di]
+ movsb
+ jmp word 0x3235:0x78b0
+ push word 0x6252
+ int1
+ or [bx+si+0xd1ef], cl
+ invalid
+ xchg cx, ax
+ jns 0x112
+ pushfw
+ jb 0x1cd
+ ficom word [0x2f0e]
+ loopnz 0x14f
+ push ax
+ xor [bx+si+0x2f], sp
+ cli
+ insw
+ les si, [si+0x2d]
+ imul bp, [bp+0x3], 0x7437
+ invalid
+ fbstp [bx+si]
+ ret 0x7e91
+ xor ax, 0x189e
+ ror word [bx+di], 1
+ xchg di, ax
+ sub ax, 0xb563
+ dec di
+ jcxz 0x13f
+ push dx
+ push ax
+ mov si, 0x268e
+ sbb ax, 0xdfba
+ pop es
+ test [bp+0x64], bx
+ xchg [bx+0xd6d], si
+ das
+ ja 0x173
+ push cs
+ pop bx
+ add [bp+di+0x4faf], dx
+ aam 0xc3
+ add bp, [0x7433]
+ ror word [di+0xbcd7], cl
+ pop bx
+ inc cx
+ dec si
+ or [0x23cf], cl
+ jae 0x22a
+ int3
+ push si
+ sbb sp, [bx]
+ jnz 0x222
+ mov dx, 0x6695
+ daa
+ xor dl, dl
+ outsb
+ shl dl, 1
+ pop bp
+ aad 0x47
+ sub [bp-0x9], ax
+ call 0x4abc
+ add al, 0x2d
+ ret 0xd5d9
+ loopnz 0x193
+ xchg bx, ax
+ or dx, [bp+si]
+ cld
+ jp 0x227
+ inc di
+ and ch, bl
+ pop ss
+ retf
+ xchg bp, ax
+ in ax, 0xf1
+ rep pusha
+ scasb
+ inc cx
+ push ss
+ pusha
+ mov ax, [0x4d9e]
+ push di
+ dec di
+ mov si, 0xd71e
+ invalid
+ xor al, 0xa3
+ xchg sp, ax
+ shl word [di+0xcece], 0x9c
+ mov bl, 0x48
+ pusha
+ test al, 0xdd
+ mov di, 0xc7d3
+ mov bx, 0x414e
+ movsb
+ or al, 0x7c
+ stosw
+ push cx
+ jnp 0x22d
+ xor bl, [bx+di+0x55b3]
+ xchg bx, ax
+ xchg ax, ax
+ dec dx
+ mov cl, 0xf2
+ xchg bp, ax
+ lock push bx
+ xchg cx, ax
+ push bp
+ les cx, [di]
+ retf
+ in ax, 0xf5
+ mov sp, 0xcad2
+ mov al, [0x4ba]
+ adc cx, ax
+ fucomi st0, st1
+ jge 0x234
+ adc di, sp
+ std
+ xor [0x9be6], di
+ invalid
+ inc sp
+ xor ax, 0x4733
+ or al, 0x73
+ jle 0x1f9
+ push ax
+ mov [0x87e4], al
+ cmpsb
+ pop di
+ sti
+ push word 0xb144
+ xor al, 0xf2
+ mov [0xb4c3], ax
+ mov bh, [di]
+ inc ax
+ mov ch, 0x87
+ add ah, dl
+ invalid
+ clc
+ lodsw
+ sahf
+ loopnz 0x2e6
+ pop bp
+ mov [0x6118], ax
+ cmp cl, [bp+si-0x3d]
+ sub dl, [bp-0x41]
+ xchg dx, ax
+ mov ax, [0x2e8f]
+ o32 fncstp
+ mov bl, 0xf0
+ mov ch, 0xf4
+ rcl byte [si-0x8], 1
+ shl word [si+0x30], 0x6f
+ aad 0x9f
+ push bx
+ mov byte [bx+0x7cb8], 0xd2
+ mov gs, [si+0x11ca]
+ in al, 0x18
+ pushfw
+ aad 0xaa
+ sbb al, 0xed
+ jmp 0x263
+ cld
+ imul si, [si], 0xbc
+ or [bp+si+0x8f31], cl
+ pop bp
+ push ds
+ add [di], dx
+ in al, 0xb4
+ out dx, ax
+ and cl, [bp+si]
+ push cs
+ push sp
+ arpl [di], dx
+ push ss
+ ret 0xd4b9
+ sar [bx+di+0x7d], cl
+ retf
+ invalid
+ mov bx, 0x8ee4
+ adc word [bp+di+0x7f44], 0xe1e2
+ o32 shr dl, 0x87
+ invalid
+ xchg cx, ax
+ adc [bx-0x4a], dl
+ scasw
+ push word [bx+0x946f]
+ cmp al, 0x9d
+ scasw
+ in al, 0x1b
+ push di
+ fdiv qword [bx+di+0x5f]
+ jae 0x2b6
+ jg 0x297
+ repne sub byte [ecx+0x9b7c0025], 0x81
+ sub di, [di]
+ cmp al, 0x1c
+ invalid
+ in al, dx
+ cmpsw
+ jp 0x299
+ inc dx
+ invalid
+ push di
+ xor [si+0x1f4a], di
+ test [bx+si+0xbd04], bl
+ in ax, dx
+ cmpsw
+ mov dl, 0xf0
+ jnp 0x35a
+ sbb [bx-0x44], cx
+ loope 0x392
+ add [di+0x81d9], cx
+ adc ax, 0xa4f0
+ hlt
+ movsb
+ into
+ sbb al, 0x2d
+ cmpsb
+ cbw
+ dec dx
+ insw
+ invalid
+ mov [0xe06f], ax
+ invalid
+ sbb ax, di
+ cmp ax, 0x5531
+ push sp
+ mov di, 0x9764
+ push di
+ js 0x381
+ jge 0x30e
+ dec ax
+ fnstsw word [bx+di-0x7f]
+ pop ds
+ shl word [bx+di], 0xe0
+ or sp, [bx+0x2926]
+ aad 0xd4
+ push di
+ arpl [bx+0x8291], bx
+ in ax, dx
+ cmp ch, ch
+ dec di
+ neg word [di]
+ a32 ret
+ pop ax
+ sbb ax, 0x6df9
+ mov cl, 0x34
+ mov dl, 0x1b
+ mov ax, [0xa1f8]
+ xor cx, [si]
+ mov bx, 0x867c
+ xor ax, 0x88d6
+ add ax, [si+0x6]
+ out dx, al
+ lodsw
+ pop ss
+ jnz 0x3b5
+ arpl di, ax
+ cmpsw
+ hlt
+ mov di, 0x2357
+ lodsb
+ xchg bp, ax
+ push bp
+ inc bx
+ pop bx
+ adc ax, 0x8bc4
+ test al, 0x8b
+ shr ax, cl
+ dec bx
+ div byte [bx+di]
+ bound bx, [bx+di-0x21]
+ fdivr dword [di+0x1a13]
+ dec bx
+ movsb
+ xor si, [bp-0x27]
+ sbb [0x89d2], dx
+ and bh, [si+0xbb3e]
+ outsw
+ and di, [bp+0xf435]
+ xor ax, 0xafd5
+ add [bx+si], dh
+ js 0x3dc
+ jmp word 0xbfdf:0x8522
+ lds sp, [bp+di]
+ jge 0x3d9
+ xchg di, ax
+ test [bx+di+0x36], bl
+ xor ax, 0xdd51
+ repne mov si, 0x5b1f
+ invalid
+ push ax
+ fstp qword [bx+si+0x4f77]
+ push si
+ jp 0x383
+ mov sp, 0x8fdc
+ fsubr qword [bp+0x35]
+ shl word [di+0x57e4], 1
+ mov di, 0xa0bc
+ nop
+ dec ax
+ fdivr st0, st2
+ popfw
+ jo 0x39f
+ daa
+ nop
+ in ax, 0xe
+ in ax, 0xc1
+ cmp [si+0x9a5d], ah
+ out 0x18, al
+ push ds
+ xchg [bp+di+0x44bd], cx
+ dec sp
+ push cx
+ pusha
+ cmpsw
+ outsw
+ inc bx
+ stosw
+ wait
+ invalid
+ mov ax, 0xf49a
+ in al, 0xbe
+ pop sp
+ mov al, 0x7d
+ cmp ax, 0x7321
+ xor al, 0xda
+ imul cx, [bx+di], 0x38aa
+ invalid
+ mov ax, 0xa09c
+ jg 0x44a
+ cmp [bp+0xb487], dh
+ stc
+ push bp
+ fild qword [bx+0x31]
+ pop ax
+ invalid
+ mov cl, 0x1f
+ clc
+ jns 0x442
+ mov bp, [bp+si]
+ in ax, 0x6
+ mov ah, 0x85
+ adc cx, [bp+di-0x1d]
+ inc di
+ jnp 0x3ed
+ xchg sp, ax
+ invalid
+ jg 0x491
+ bound dx, [si]
+ adc si, bx
+ mov ch, 0xc3
+ push sp
+ inc cx
+ dec bx
+ jle 0x3db
+ test [di+0x5122], ax
+ push word 0xf672
+ push dx
+ push ax
+ mov [0xd9be], al
+ cmp ch, [bp+di+0xf270]
+ jmp 0xa4e
+ inc si
+ add al, 0x6f
+ mov [0x9ce8], ax
+ leave
+ mov cx, 0xebad
+ jbe 0x494
+ shl word [bx+di+0xac9b], 1
+ or ax, 0x158e
+ int1
+ sub bl, bh
+ lodsw
+ and al, 0x52
+ mov cl, al
+ push dx
+ and ax, 0x662
+ add ax, 0xecf6
+ push si
+ jmp 0x4f3
+ push bx
+ cld
+ or al, 0xe4
+ jnz 0x4bd
+ shl byte [bx+si], 1
+ mov cx, 0x583c
+ mov [0xbc10], al
+ fidiv dword [bp+si]
+ adc al, 0x8c
+ jp 0x4af
+ popa
+ inc si
+ jmp word far [bp+di+0x2715]
+ jmp 0x4a2
+ int 0xbb
+ dec di
+ outsw
+ mov dl, 0x55
+ sbb al, 0xbb
+ xchg sp, ax
+ sbb ax, 0xa77e
+ push dx
+ a32 and ax, 0xd401
+ mov ax, [0xf7d7]
+ enter 0x5092, 0xcf
+ retf 0xbec1
+ lock into
+ jp 0x453
+ into
+ mov bh, 0xf7
+ and al, 0x80
+ cmp [si], dh
+ nop
+ in ax, 0xcf
+ xor [0x3daf], ch
+ mov [si], di
+ sub byte [bp+di], 0x88
+ xor [bp+0xf5b9], bh
+ mov al, [0x7e59]
+ cwd
+ hlt
+ aaa
+ movsb
+ lea si, [bp+di+0x8281]
+ inc dx
+ xor bx, [bx]
+ mov sp, 0xcb8f
+ ja 0x4fc
+ wait
+ repne push si
+ adc al, 0xb7
+ inc cx
+ inc bx
+ dec si
+ wait
+ cmp ax, 0xa78a
+ push word 0xdd84
+ call word 0x97e9:0x3040
+ aam 0x7
+ mov [0x23a1], ax
+ jo 0x53d
+ retf
+ sbb di, [bx+si+0x49d3]
+ mov sp, 0x9fff
+ mov bh, 0x3a
+ pushfw
+ cmpsw
+ mov ah, 0xad
+ or dh, [bp+si]
+ push ss
+ inc dx
+ xor [bx+di], cx
+ mov di, 0x147
+ inc sp
+ mov ax, [0x4339]
+ jcxz 0x4f7
+ inc sp
+ mov ah, 0x90
+ and [si+0xb08a], ah
+ xchg bp, ax
+ sbb bp, bx
+ mov bl, 0x42
+ xchg [di-0x1f], di
+ xor ax, 0x2d90
+ push es
+ and si, ax
+ add bl, [bp+di+0x2]
+ popfw
+ leave
+ sar word [bx+di-0x61], 0x7d
+ jp 0x4f2
+ xchg bx, ax
+ mov cx, 0xe5d
+ jo 0x5cd
+ fsub dword [bx+si+0x11eb]
+ fidivr word [bx+si]
+ scasw
+ stc
+ xchg si, ax
+ mov al, [0x36a2]
+ std
+ dec si
+ sti
+ invalid
+ xor al, 0xe7
+ test byte [di], 0xcd
+ insb
+ imul word [bx+si]
+ dec sp
+ push ss
+ rep inc si
+ cmpsw
+ leave
+ pop di
+ jcxz 0x52d
+ retf 0x3450
+ mov ch, ah
+ movsw
+ stosb
+ sti
+ or bl, [bp+di+0x4199]
+ movsw
+ push ds
+ mov al, [0xc0d6]
+ cmp al, 0x38
+ xchg bx, ax
+ dec bp
+ dec di
+ dec dx
+ dec dx
+ add [bx+si], cx
+ adc al, 0x6e
+ inc ax
+ leave
+ adc al, 0x26
+ jmp 0x556
+ invalid
+ insw
+ pusha
+ bound sp, [si]
+ invalid
+ ja 0x5b1
+ scasb
+ xchg sp, ax
+ invalid
+ repne inc di
+ dec bp
+ cmp ax, 0xbcd0
+ jl 0x629
+ cmp dh, bh
+ or dx, si
+ jo 0x55b
+ xor al, 0x9b
+ test byte [di+0x164], 0x74
+ mov bp, 0xa3e9
+ jp 0x5aa
+ jmp 0x5898
+ rep push dx
+ mov al, 0x77
+ mov cl, 0xda
+ mov dl, 0xec
+ insw
+ scasb
+ xchg cx, ax
+ rol bh, 1
+ and ax, 0xad88
+ mov byte [bx-0x6], 0x3e
+ out 0x66, ax
+ ja 0x5f0
+ mov [0xa31c], al
+ dec bp
+ sar [bp-0x76], cl
+ push es
+ jae 0x5f5
+ ja 0x623
+ adc bx, cx
+ xchg bx, ax
+ xlatb
+ cwd
+ pop ds
+ sahf
+ mov bx, 0x5910
+ xor al, 0xff
+ mov al, [0xf4c1]
+ enter 0x1f5e, 0xa6
+ call 0x2d83
+ aas
+ jns 0x5b9
+ mov bl, 0x7a
+ adc si, ax
+ jmp word 0x103b:0x24f4
+ adc al, 0xce
+ inc cx
+ rep fstp qword [bx+si+0x23]
+ out dx, eax
+ jno 0x59b
+ imul sp, bp, 0xfd
+ or [di+0x5ba2], ah
+ inc sp
+ scasb
+ jcxz 0x5d4
+ cmp bh, ah
+ in ax, dx
+ aas
+ nop
+ sbb al, 0xd8
+ call word 0x79d8:0xc271
+ mov dh, 0x43
+ inc di
+ inc sp
+ popfw
+ das
+ pop di
+ in al, 0xa8
+ xchg bx, ax
+ mov dh, 0x9f
+ invalid
+ out dx, ax
+ nop
+ test ax, 0x741d
+ fldcw word [bp-0x5f]
+ adc [bx+di+0x34], cl
+ push bx
+ test si, 0x2761
+ popa
+ out dx, ax
+ adc bx, [bp+si+0x48a9]
+ fptan
+ sub al, 0x46
+ mov ax, 0xc441
+ inc byte [bp+di+0x9db1]
+ scasw
+ cmp si, ax
+ sub [bx-0x66], ax
+ dec bp
+ cmp bl, 0x61
+ mov al, [0xebf3]
+ out 0x25, al
+ inc cx
+ pusha
+ movsw
+ int3
+ test al, 0xc0
+ mov cl, 0x39
+ insw
+ jmp 0x627
+ add ax, 0x295d
+ o32 fidivr dword [bx+di]
+ jg 0x6a2
+ push ax
+ sub al, 0x5e
+ sbb cx, [bx+si]
+ xchg cx, ax
+ dec bp
+ out 0xe2, ax
+ pop bx
+ jp 0x653
+ jmp word 0xfa79:0xaa3b
+ jns 0x6c1
+ shl byte [bp+si+0xe325], 1
+ mov ecx, 0x56cadec
+ or di, [bx+di+0x4e2e]
+ cmp al, 0xfb
+ sub ax, 0xa8d8
+ repne push dx
+ mov cx, [bp+0x8]
+ and cx, [bx+si+0xf452]
+ clc
+ mov cx, 0xd7d8
+ int1
+ mov si, 0x5708
+ or ax, 0xbd70
+ mov ax, [0x8e58]
+ adc sp, [ecx]
+ adc word [bx+si], 0xbf
+ and word [si], 0x94
+ invalid
+ sub ax, 0xa2af
+ pop ds
+ sahf
+ mov cx, 0x29ae
+ fstp9 st4
+ clc
+ cmp cl, cl
+ cmc
+ enter 0x4f3f, 0xf8
+ adc byte [bp+si+0x8e71], 0x4b
+ jmp 0x699
+ loop 0x6ad
+ jz 0x66e
+ aam 0x1b
+ push bx
+ call 0x3204
+ test [bp+0x62], ch
+ test al, 0x70
+ enter 0xabbc, 0x1a
+ out 0xd4, ax
+ or cl, [di]
+ insb
+ aas
+ sbb bl, [bp+di]
+ in ax, 0x7c
+ sbb ax, 0x4d07
+ mov cx, 0x6db9
+ mov bl, 0x8a
+ push 0xf9
+ sbb cx, [bx+si+0x669e]
+ xor [bp+di], bx
+ mov si, 0x5b3d
+ fcomp5 st1
+ js 0x6fc
+ sbb ax, 0xe0d5
+ inc word [0xa87d]
+ insb
+ inc bp
+ ret 0xda6
+ mov sp, 0xba3b
+ jmp 0xffffffffffff9862
+ jle 0x793
+ mov dx, 0xd8e3
+ or ax, [si+0xd1b6]
+ les si, [bp+si]
+ test al, cl
+ int1
+ fld qword [di]
+ cli
+ adc bx, ax
+ jle 0x7a4
+ jae 0x758
+ pop si
+ das
+ hlt
+ jbe 0x731
+ jge 0x78e
+ ret
+ in al, dx
+ lodsw
+ ja 0x74e
+ pop bx
+ scasw
+ cld
+ mov bh, 0xa0
+ adc ah, [bx+si]
+ sbb al, 0x53
+ imul ax, [bx+di+0x938a], 0x9b0e
+ fmul qword [bx+0x74]
+ push bx
+ cmpsb
+ xchg [bp+si+0x5082], bp
+ xchg cx, ax
+ inc bx
+ imul byte [bp+si-0x5d]
+ lahf
+ add ax, 0xadde
+ xchg [bx+si+0xc], ah
+ sti
+ or ax, 0x6d7b
+ xchg dx, ax
+ mov al, [0xe4ed]
+ jbe 0x73d
+ int1
+ xlatb
+ fidiv dword [0x1788]
+ inc al
+ mov [bx+di+0x6253], sp
+ inc di
+ cbw
+ xlatb
+ mov dx, 0xea50
+ stosw
+ push sp
+ jo 0x7ae
+ add dh, [bx]
+ fsub qword [bx+di]
+ xor [si+0xf], bp
+ dec ax
+ lahf
+ arpl [bp+si-0x4b], bp
+ invalid
+ clc
+ mov sp, 0xa834
+ mov bx, 0xfd9c
+ jcxz 0x7a0
+ dec di
+ add bp, [bx-0x40]
+ mov dx, 0xa522
+ pop ss
+ xchg di, ax
+ sub [si], ch
+ mov sp, 0xbc9f
+ sbb [bx-0x17], cl
+ inc di
+ xchg [ds:0x559c], si
+ cmp dx, [bx]
+ jz 0x834
+ xchg sp, ax
+ dec cx
+ salc
+ push cx
+ aad 0xf9
+ inc byte [bp+si+0x8bf5]
+ cld
+ push bx
+ sbb ah, [bp+0x9e65]
+ push es
+ push cs
+ shr dx, cl
+ in al, dx
+ pop ss
+ xchg sp, ax
+ and [bp+si], cx
+ dec cx
+ wait
+ daa
+ jle 0x779
+ push ds
+ mov [bx+di-0x65], ah
+ inc ax
+ pop es
+ jnp 0x7f4
+ jmp 0xffffffffffffdc25
+ push ds
+ jae 0x86b
+ mov [0xbab1], ax
+ xor ax, 0xd376
+ adc dx, [bx+0x7a]
+ jg 0x838
+ inc ax
+ salc
+ xor word [bx], 0xb7cd
+ push si
+ mov si, 0x879
+ xchg di, ax
+ in al, dx
+ ret 0xfc88
+ xchg sp, ax
+ outsw
+ mov cx, 0x9fe0
+ invalid
+ outsw
+ popfw
+ inc dx
+ push sp
+ xchg cx, ax
+ mov cx, 0xb740
+ repne aas
+ adc ax, 0x7f6a
+ iretw
+ mov ah, 0x63
+ sahf
+ jnp 0x876
+ mov bp, 0xffbb
+ sbb al, 0x3d
+ jmp 0xffffffffffffac8f
+ arpl [bp+di+0x4d45], cx
+ push si
+ pusha
+ or ax, [di-0x14]
+ push si
+ sbb ax, 0xc0ae
+ invalid
+ dec ax
+ and al, [bx-0x3b]
+ push cx
+ aaa
+ xchg [bx+di+0x6b], sp
+ fcmove st0, st4
+ jmp word 0x34ff:0x9395
+ and bp, [bx+si]
+ adc al, bh
+ xor ax, 0x2ee2
+ fadd qword [bx+si]
+ add [bp+di+0xd786], ax
+ cld
+ push bp
+ jg 0x88e
+ jmp 0xffffffffffffccf7
+ fisttp qword [bx+si+0xfc5d]
+ in al, dx
+ and cx, [bp+0xf6fd]
+ adc al, 0xf3
+ xor [bp+0x8], al
+ fstp qword [bx+si-0x6e]
+ ja 0x803
+ add byte [bx+si+0x8a1f], 0xef
+ imul dx, [bx+0x106e], 0x6d
+ mov ch, 0x59
+ sub si, [di]
+ in ax, 0xf4
+ jg 0x8b3
+ stc
+ mov [bp+di], ds
+ or word [si], 0x42dc
+ out dx, al
+ arpl [0x2f50], ax
+ fsubrp st5, st0
+ jl 0x909
+ loop 0x832
+ mov sp, 0xb4a6
+ mov si, 0x1534
+ cmp [bx+si+0x74], bl
+ invalid
+ jno 0x8e0
+ jmp word 0x9127:0x8a2b
+ push cx
+ pop sp
+ sbb [bx+0x5cc1], cx
+ retf 0xd633
+ or ax, [bp+si+0x0]
+ das
+ movsw
+ cmc
+ cmpsb
+ add [si-0x7d], ch
+ adc [si-0x79], si
+ and [di-0x2d], bp
+ dec ax
+ retf
+ sbb [bx+di], dl
+ mov dh, 0x35
+ rcl word [bx-0x1f], cl
+ or [si+0x60], dh
+ enter 0x211f, 0x78
+ shl word [bx+di+0xe3c8], 1
+ ja 0x900
+ out 0x82, al
+ o32 loop 0x90a
+ invalid
+ cmp [0x921a], dl
+ rcl word [bx+si+0x55], cl
+ cmc
+ jbe 0x93a
+ leave
+ adc dx, [bp+di]
+ mov cl, 0xbb
+ push bx
+ and ax, [si-0x20]
+ or cl, bh
+ outsw
+ xor [bp+0xd0e8], dx
+ hlt
+ adc [di], bh
+ cwd
+ xlatb
+ cmc
+ sbb al, 0xc5
+ inc ax
+ loop 0x8f9
+ jbe 0x937
+ dec di
+ and bp, bx
+ sbb al, [bx+si+0xb12]
+ mov [bx], ch
+ pop di
+ nop
+ xchg sp, ax
+ sti
+ invalid
+ arpl [si+0x77e1], sp
+ pop ds
+ fidiv dword [bx+di]
+ mov al, [0x71b]
+ mov ax, 0x9abd
+ jnp 0x8ff
+ pop ax
+ push cs
+ pop dx
+ sub ax, 0x3f5c
+ pop ss
+ fcmove st0, st3
+ and ax, 0x4aa9
+ a32 jno 0x8d7
+ adc ch, ch
+ or si, [bx+di]
+ xor bl, [si-0x3]
+ wait
+ aaa
+ xlatb
+ inc ax
+ sub [bx+si], bh
+ jnz 0x8d3
+ jmp word 0xf1be:0x2348
+ invalid
+ movsb
+ or bx, [ss:bx+si+0x2d]
+ adc bp, bx
+ adc [bp+0xd235], cx
+ pop ds
+ xchg bp, ax
+ mov [bp+0x3f], ax
+ ja 0x957
+ sub sp, dx
+ xor word [bx], 0xa7
+ loop 0x936
+ std
+ mov bh, [bx+di+0x9152]
+ mov ah, 0x46
+ in al, dx
+ mov dl, 0x45
+ xchg dx, ax
+ push 0xc5
+ wait
+ pushfw
+ sti
+ in al, dx
+ jge 0x901
+ jbe 0x9be
+ xchg dx, ax
+ inc di
+ xchg dx, ax
+ cmp ch, cl
+ loop 0x9d3
+ dec cx
+ lodsw
+ pop bx
+ xchg [bx+0x9360], ah
+ dec ax
+ stosw
+ js 0x96e
+ mov cx, 0xa604
+ fsubr qword [bx+0xceab]
+ adc si, [bx+di+0xd828]
+ pop ss
+ scasb
+ rcr byte [di+0x3a], 1
+ sub [bx+di], ax
+ mov bp, 0x42cb
+ sar di, cl
+ and ah, ch
+ push sp
+ loope 0x9b4
+ dec bp
+ xor dl, bl
+ out dx, al
+ mov [bx], si
+ jl 0x982
+ invalid
+ fld qword [di-0x7c]
+ insw
+ wait
+ dec di
+ push di
+ adc bx, [bp+si-0x27]
+ salc
+ xor word [bx+di], 0x5c
+ dec byte [bp-0x3f]
+ or [bp+si], ax
+ xchg dx, ax
+ into
+ outsw
+ xor [bx+0x4b77], dx
+ xor [si+0x548d], ax
+ imul si, bx, 0xdfba
+ mov sp, 0xbe94
+ mov cx, 0x367e
+ adc al, 0x13
+ push ss
+ lock shl byte [bp+di], 0x56
+ mov [bp+0x4c6c], ss
+ dec bx
+ sbb si, sp
+ mov bx, 0xc129
+ or al, 0xaf
+ jno 0xa19
+ das
+ dec si
+ popfw
+ xor [bx+di+0x88f6], sp
+ or [di], bp
+ wait
+ mov ax, [0x9891]
+ mov di, 0x5cbf
+ popa
+ add dl, [bx+si+0x5d02]
+ jl 0x9c8
+ xlatb
+ push cs
+ iretw
+ std
+ int3
+ stosw
+ shl word [bp+si-0x34], 1
+ cmp dl, dh
+ jno 0xa01
+ adc dl, [bp+si+0xac71]
+ jno 0x9bc
+ salc
+ push cx
+ int3
+ jmp word 0xdd39:0x9c2e
+ jle 0x9e2
+ cmp byte [bx+si], 0x67
+ pop di
+ jle 0xa98
+ in al, 0x2f
+ adc [bp+di], ax
+ idiv bp
+ push es
+ lea bp, [bp+si-0x6e]
+ inc bp
+ pop si
+ xor [di], sp
+ in al, 0x8c
+ out dx, al
+ sbb dh, [si+0x67]
+ into
+ sahf
+ shl word [bp+0x47], 0xf0
+ movsw
+ inc bp
+ rol word [bx+di+0x2a6a], 1
+ adc al, 0x1b
+ int3
+ mov cl, 0x8a
+ lock repne cmp ax, bp
+ mov [si], al
+ fiadd word [si]
+ xchg cx, ax
+ arpl [bx], dx
+ jnz 0xa6c
+ push cs
+ adc cx, [bx+0x7a]
+ jp 0xa88
+ aaa
+ push bx
+ mov [di-0x32], bh
+ or al, 0x23
+ iretw
+ inc dx
+ psubusb mm7, mm4
+ jcxz 0xaaf
+ das
+ das
+ xchg bx, ax
+ mov dl, 0x8e
+ test al, 0xcd
+ invalid
+ adc al, 0x5b
+ sbb ax, 0x660b
+ or [bx], al
+ repne shl al, 0xf5
+ pop es
+ salc
+ xchg bx, ax
+ imul ax, [bp+di], 0x9ea2
+ aam 0x59
+ xchg cx, ax
+ dec cx
+ invalid
+ adc al, ah
+ jmp word 0xe423:0x4f72
+ call 0xffffffffffff907e
+ sub ch, bl
+ jns 0xa40
+ xor byte [bx+si+0xefc], 0x75
+ out dx, ax
+ mov cx, 0xb0a2
+ int1
+ mov dx, 0x9439
+ std
+ popa
+ fbstp [si]
+ test ax, 0x2e4b
+ movsb
+ in al, dx
+ mov cx, 0x6992
+ in al, 0x8e
+ inc sp
+ mov dx, 0x610b
+ cmp ax, 0x85f7
+ sbb al, 0x1b
+ insw
+ mov ch, 0x66
+ sbb ax, [bp+si+0x3107]
+ cmp [bp+si+0xc8e8], bx
+ o32 jz 0xaca
+ btc [bx+di], di
+ pop ss
+ jl 0xb20
+ jcxz 0xb2f
+ scasw
+ cmpsb
+ lahf
+ push ds
+ add al, 0x97
+ pushfw
+ salc
+ aad 0x6
+ popa
+ aam 0x72
+ enter 0xfba7, 0x60
+ out dx, ax
+ mov [bp+si+0x43], ax
+ inc bx
+ xor ax, 0x4a48
+ pusha
+ add ah, bl
+ jnz 0xae4
+ cwd
+ and ax, 0x52e6
+ add al, 0xe7
+ lahf
+ push ds
+ jz 0xb01
+ push bx
+ or sp, [bp+di-0x16]
+ fbstp [bx]
+ xor word [si+0x7f36], 0x920d
+ pop dx
+ jb 0xb2a
+ mov ax, bx
+ lds ax, [bp-0x2f]
+ inc ax
+ clc
+ push word 0x87ab
+ div word [di+0x2d39]
+ cli
+ xchg bp, ax
+ jle 0xadd
+ dec bp
+ test [bx+0xb13c], sp
+ mov dh, [si+0x1e]
+ and dl, [0xbc86]
+ shr ch, 0x52
+ push word 0x5836
+ in ax, dx
+ stosb
+ popfw
+ cli
+ inc bx
+ jmp word 0x1549:0xa128
+ adc bl, cl
+ fisub dword [bp+si]
+ pop di
+ sahf
+ std
+ jnp 0xafd
+ push word 0xdb7
+ jl 0xbb1
+ push di
+ daa
+ int3
+ mov ch, 0xb4
+ adc ax, 0x4747
+ jz 0xb52
+ mov dh, 0x9b
+ dec sp
+ jns 0xbcd
+ std
+ xor dh, al
+ push dx
+ mov bp, 0x4ff4
+ adc dx, [di+0x2432]
+ dec ax
+ jg 0xbab
+ push ss
+ test [bp+si+0x3694], cx
+ nop
+ jmp word 0xb9f2:0xacf3
+ sahf
+ pushfw
+ cmp di, [bx+di-0x7]
+ stosw
+ adc dh, 0x3e
+ sbb al, 0x4
+ mov [0xf994], al
+ ret 0x72cb
+ cmpsb
+ pop ds
+ pop ss
+ sar word [di], 0x47
+ imul di, [bx+si], 0x44
+ mov si, 0x9922
+ imul ax, si, 0x6f
+ clc
+ mov ch, 0x93
+ pop dx
+ int 0x82
+ xchg di, ax
+ mov bl, [bp+di-0x56]
+ stosb
+ call word 0xb4d:0xb446
+ or byte [bx+0xa], 0x6d
+ mov bh, [bx+si-0x62]
+ or [si+0x4d30], cx
+ scasb
+ sbb bh, [bx]
+ jp 0xb5b
+ movsw
+ outsb
+ nop
+ sub cx, [bp+si]
+ inc bp
+ out dx, al
+ sub ax, [bp+si]
+ stc
+ pop di
+ adc al, 0xbf
+ repne mov ax, [0xf35]
+ pop di
+ aam 0x75
+ arpl si, bp
+ fsubr dword [bp+di+0x1d]
+ mov sp, 0x6e72
+ imul sp, ax, 0xc978
+ or [bx+si], bp
+ pop es
+ lock and [bp+di+0x55], ch
+ test al, 0xca
+ cmpsw
+ xor al, 0xdb
+ dec si
+ lock mov cl, bl
+ pop bp
+ call word 0xe705:0xbccd
+ jo 0xc3b
+ dec sp
+ mov ch, 0x50
+ xlatb
+ test [bx+si+0x487a], ax
+ in al, 0x66
+ or ax, 0x61f4
+ adc bl, dl
+ call 0xffffffffffffa133
+ inc bp
+ mov cx, 0x9af2
+ jle 0xbde
+ pop bx
+ or word [si], 0x5450
+ pop dx
+ jcxz 0xbdf
+ fisubr word [bp+si]
+ popfw
+ out dx, ax
+ and [0x23bb], bh
+ xchg si, ax
+ or [bx+si], cl
+ push dx
+ jo 0xc82
+ xor ch, [bp+si+0x4]
+ jb 0xc04
+ inc bx
+ cmc
+ neg byte [bp-0x53]
+ pop dx
+ sbb al, 0x3f
+ lds di, [bx+di+0x4356]
+ test al, 0xaf
+ nop
+ mov al, 0xb5
+ or byte [bx+si+0x71], 0x43
+ xchg dx, ax
+ aam 0x63
+ call word 0xed2e:0xc16a
+ aaa
+ out dx, al
+ adc ax, 0xa4b9
+ xchg di, ax
+ test al, 0x67
+ jz 0xc46
+ movsb
+ imul si, [bp+0xc5a1], 0xfb
+ push bx
+ pop dx
+ jg 0xbda
+ or byte [bx+0x7649], 0x36
+ lahf
+ jge 0xca9
+ imul di, [bx+si], 0xa59b
+ dec dx
+ sub al, 0x28
+ pop bp
+ and bx, [ds:bx+di+0xd08]
+ mov dh, cl
+ inc sp
+ sub [di+0x11], cx
+ pop sp
+ dec cx
+ push bp
+ salc
+ mov ah, 0x36
+ jge 0xc35
+ jnp 0xcb2
+ pop dx
+ inc cx
+ inc bx
+ or ch, al
+ sub [bp+di], ch
+ o32 jb 0xcf9
+ das
+ sub ax, 0x2927
+ ret
+ invalid
+ xor dl, ch
+ invalid
+ inc bp
+ out dx, al
+ xchg bx, ax
+ int 0x3c
+ arpl [bx+di+0xdfe3], di
+ wait
+ fadd st0, st5
+ lock invalid
+ xchg al, ch
+ add ax, 0xd371
+ sahf
+ xor ax, 0x872a
+ invalid
+ xor ch, [bx+di-0x15]
+ invalid
+ push cs
+ xor dh, [bx]
+ arpl [si], cx
+ jl 0xc5a
+ dec si
+ fbld [si+0x49]
+ rep pop ax
+ pop di
+ add word [bx+0x6c2a], 0xca
+ push si
+ adc ax, 0xc6ae
+ cli
+ sbb ax, 0x404f
+ inc sp
+ cmpsw
+ int 0x66
+ sbb [0x3621], si
+ invalid
+ sub bh, cl
+ call 0x8c3f
+ mov bp, 0x12c8
+ push ds
+ stosw
+ jz 0xcf3
+ rol ah, 1
+ int1
+ mov bl, 0x4b
+ push es
+ or al, 0xd5
+ imul cx, [bp+si+0x7bd3], 0x1c18
+ call 0x88ec
+ outsw
+ sbb di, bp
+ push bx
+ test al, 0x4a
+ fidivr word [bp+di+0x72e7]
+ aam 0xdb
+ mov [0x3ac4], ax
+ push ds
+ cli
+ xchg di, ax
+ ret
+ push dx
+ push di
+ push ss
+ dec si
+ adc al, ch
+ wait
+ cwd
+ out dx, al
+ test [bp+di+0x8cac], cx
+ mov ax, bx
+ fcom dword [bx+si-0x25]
+ stosb
+ lahf
+ a32 mov bx, 0x1d22
+ jmp 0xd06
+ rcl byte [bx+di+0xc686], 1
+ test ax, 0xc9cc
+ and dh, [bx+0xe867]
+ lahf
+ adc bl, cl
+ mov di, 0xaa58
+ test [si-0x4], bh
+ cmp sp, bx
+ xchg [bp+di-0x6a], dx
+ push ds
+ mov cr1, [di+0x1b]
+ push ss
+ cli
+ xor cx, [bx+si+0xca8e]
+ pop sp
+ fdiv qword [bp+si-0x1e]
+ imul bx, bx, 0x6844
+ xchg di, ax
+ xor [di], bl
+ retf
+ ret 0xd37
+ das
+ inc ax
+ xor word [0xcb00], 0x1db6
+ mov cl, 0x2c
+ mov [bp-0x6f], di
+ leave
+ mov [bp+di], bh
+ imul ax, [0x630a], 0x894b
+ add ax, [bp+0x65]
+ xchg di, ax
+ sub di, dx
+ inc si
+ repne or bp, [bx+si-0x58]
+ loope 0xcfb
+ sub ax, 0x573e
+ lahf
+ dec bx
+ lea dx, [bx]
+ in al, 0x80
+ jae 0xd7d
+ xchg di, ax
+ sbb al, 0x22
+ sbb byte [bx+0x1637], 0xc6
+ xchg si, ax
+ push dx
+ jno 0xda6
+ pop es
+ dec sp
+ ret 0xc7e4
+ push ss
+ fbld [bp+di]
+ mov di, 0x479b
+ lodsw
+ adc dl, dh
+ sahf
+ sbb ch, [bx+si+0xe4c7]
+ mov dh, 0x39
+ fmul qword [bx+di+0xc8c2]
+ adc al, 0x7b
+ xchg di, ax
+ int1
+ mov bx, [si]
+ xor di, bx
+ enter 0x5f41, 0x9d
+ xor ax, 0xd870
+ mov ch, 0x78
+ mov sp, 0x7c3b
+ stosb
+ jb 0xdf5
+ scasw
+ and byte [bp+0x2fdc], 0xd3
+ jz 0xdec
+ hlt
+ std
+ xor al, 0x1d
+ inc si
+ or ax, 0x5706
+ adc ax, [si+0x60f1]
+ out 0xfe, al
+ test byte [bx+si-0x6c], 0x2f
+ arpl [bp+0x37], bp
+ or al, 0xa8
+ xor [bp+si], ah
+ xchg si, ax
+ xchg cx, ax
+ add [bp+si+0x8], al
+ jl 0xdf6
+ ficom dword [0x2180]
+ mov si, 0xfd24
+ test si, si
+ sub al, 0x33
+ int1
+ jbe 0xe3c
+ push cs
+ xor al, 0x89
+ mov bp, 0x9942
+ jmp word 0xe375:0x5124
+ invalid
+ retf
+ inc dx
+ scasb
+ or byte [bx+di-0x5e], 0x10
+ fimul dword [bx+0x76]
+ imul bp, [di+0xa334], 0x8532
+ rdtsc
+ adc ax, [gs:di]
+ push 0x75
+ xchg dx, ax
+ mov bh, 0x9f
+ mov ax, 0x540d
+ jae 0xde4
+ xor ax, 0x4f52
+ adc al, 0xd
+ rol byte [di+0x556b], 0x95
+ lds bx, [bx]
+ jae 0xea7
+ xor [bp+0x58], bx
+ or bl, [bx+di]
+ and bx, [bp+si-0x6]
+ test [bx+0xb0c5], dh
+ sub cl, [bp+di+0x23]
+ mov sp, 0x9561
+ or al, 0xe4
+ invalid
+ mov al, [0x47be]
+ movsw
+ dec bp
+ and di, [di+0x71]
+ xlatb
+ lock jbe 0xec9
+ mov ch, 0xa9
+ cmp [bp+si+0x52], sp
+ xor al, 0x22
+ pop es
+ sub dh, 0x45
+ sub ax, 0xd79d
+ xor al, 0xb2
+ mov bh, 0x55
+ mov cx, 0xc2c1
+ xor ch, [0xb58]
+ adc cx, 0x8e
+ lodsb
+ add [bx], ch
+ sub ax, 0x5fde
+ dec di
+ mov [bx+si-0x4f], bp
+ sbb cl, [bp-0x20]
+ stosw
+ out 0xbc, ax
+ pop bp
+ and ax, 0x8d00
+ or byte [bx-0x70], 0x53
+ xor al, 0x20
+ jno 0xe8c
+ sbb word [bp+di+0xe924], 0x23c
+ jle 0xeb2
+ test ax, 0xb2f8
+ or bx, sp
+ fiadd word [bp+di-0x12]
+ sub [bp+di+0x86ca], dx
+ sbb [bp+si], ch
+ ficomp dword [bx+di+0x59e8]
+ push dx
+ cmp [si], bp
+ and sp, 0xdc
+ pop si
+ not word [bp+si+0x49]
+ lodsb
+ in al, 0x43
+ push ds
+ mov [0x276e], ax
+ mov ah, bh
+ pop dx
+ call word 0xefb5:0xd5e5
+ repne mov [0x7a9a], ax
+ and [bp+si], ax
+ cli
+ mov sp, gs
+ mov [0x76c2], ax
+ out 0x86, al
+ nop
+ cmp dh, [di]
+ mov [gs:0x2711], al
+ add dh, dl
+ cmpsw
+ ficomp dword [bx+di+0xbcdf]
+ xchg bx, ax
+ arpl [bx+di+0xfa51], si
+ popfw
+ push ss
+ push bp
+ adc [di+0x8571], ah
+ inc bx
+ nop
+ add bp, bx
+ maskmovq mm2, [bx+si-0x17]
+ js 0xee5
+ mov dl, bh
+ push di
+ push di
+ shr ax, cl
+ or ax, 0x312c
+ call 0xffffffffffffa21b
+ dec di
+ sbb al, 0x80
+ and si, [bx+di]
+ test al, 0x14
+ pusha
+ ret
+ inc cx
+ adc [bp+0x3b], sp
+ invalid
+ cmp bx, [bx+di-0x34]
+ rol byte [bp+0x9d74], cl
+ jnp 0xf55
+ sbb ax, bx
+ cwd
+ push bx
+ invalid
+ ja 0xf88
+ dec si
+ invalid
+ adc ax, 0x79c6
+ std
+ xor ax, 0x879b
+ lodsw
+ pop bx
+ stc
+ sbb dl, [si+0xa0df]
+ xchg si, ax
+ xchg di, ax
+ inc si
+ jcxz 0xed6
+ mov [bp+si+0x22], cr0
+ xchg di, ax
+ imul si, di, 0x3f5f
+ mov ch, 0xa2
+ push ax
+ cmp [si], sp
+ test ax, 0x1e62
+ or si, di
+ loope 0xf83
+ outsw
+ call 0xffffffffffffa13d
+ int1
+ xchg si, ax
+ invalid
+ sti
+ mov cx, 0x610f
+ mov cx, 0x9f2b
+ and bh, [bp+di+0x9c08]
+ hlt
+ dec bx
+ imul word [bp+di-0x19]
+ test al, 0x67
+ shl word [bp+si], 0x17
+ in ax, 0xfd
+ wait
+ cmp ax, 0xf37f
+ push ss
+ or [bx+di], dl
+ sub [bx+si-0x31], ch
+ fmul dword [di-0x7c]
+ sub al, [bx+di]
+ stosb
+ shr word [bx+si+0x4de7], 0x99
+ pop dx
+ or ax, 0xbf41
+ dec sp
+ out 0x35, al
+ cbw
+ add [bx-0xa], ch
+ sub al, 0x99
+ jle 0xf79
+ push si
+ cmpsb
+ inc cx
+ sub word [fs:si+0x60], 0x8968
+ insb
+ int1
+ jle 0xfc3
+ jbe 0xf47
+ cmp al, 0xa4
+ ror byte [bp+0x5502], 0x0
+ dec bp
+ or [bp+0xe7f7], ch
+ aaa
+ out 0x11, al
+ or ah, [bx+0x927a]
+ in ax, 0x7e
+ fxch4 st1
+ pop cx
+ add al, 0x60
+ inc bp
+ pusha
+ xor bl, [bp+di+0x87ce]
+ rep xor ax, 0x8702
+ jcxz 0xf42
+ sbb byte [si], 0x9e
+ sub si, cx
+ invalid
+ dec dx
+ outsb
+ and al, 0x50
+ popfw
+ pop bp
+ int 0x92
+ rcl word [di+0xc430], 1
+ neg word [bx+di]
+ iretw
+ mov [0xd961], al
+ adc al, 0x98
+ push ss
+ stosw
+ mov al, [0x4d13]
+ inc sp
+ out 0x29, al
+ xchg bx, ax
+ sub bl, [bx+si]
+ idiv si
+ sub ax, 0x971c
+ ror byte [bx+0x3652], 1
+ sbb cx, sp
+ retf 0x3ab0
+ xor al, 0x97
+ adc [bx+si], di
+ jle 0xf8d
+ adc [bp+di+0x2e1d], di
+ lodsb
+ adc dl, cl
+ sar word [bp+di-0x57], cl
+ fist dword [si-0x9]
+ popa
+ ja 0xfb0
+ scasw
+ push ax
+ mov sp, 0x5827
+ cmovle cx, [bx-0x7]
+ invalid
+ jnp 0x1027
+ xchg sp, ax
+ push bx
+ push di
+ jnz 0x105f
+ mov [0x4468], ax
+ wait
+ xchg dx, ax
+ sub al, 0x57
+ and word [si+0x56b6], 0x296
+ push cs
+ shr [bp+si-0x75], cl
+ jno 0xfc1
+ clc
+ aas
+ xchg cx, ax
+ jmp 0xffffffffffffe25f
+ inc byte [bx+di-0x39]
+ fadd dword [bx+si+0xc3c]
+ rcr byte [bx+si+0x4d], 1
+ jp 0x1051
+ outsw
+ test al, 0x78
+ mov bh, 0xd3
+ out 0x69, ax
+ mov [0x1122], al
+ o32 cmp dl, ch
+ neg word [si+0x31]
+ popa
+ mov cl, 0xcf
+ dec di
+ mov [bx+si], ds
+ mov [0xce77], al
+ mov [bp+0x13], sp
+ cmp byte [bx+si+0x8b3], 0x9b
+ sbb [bx+di], si
+ shr sp, cl
+ js 0x1035
+ jmp 0xc2f
+ and [bx+si], ah
+ aas
+ cmpsw
+ jge 0x1090
+ mov [bx+0xaac3], cr1
+ inc bp
+ test [fs:bx+si+0x57], bp
+ push ax
+ in al, 0x10
+ int3
+ loope 0x1051
+ jns 0x1054
+ call 0x8508
+ hlt
+ lea si, [si+0xd17c]
+ cmp al, 0x2
+ mov si, 0xdbe8
+ fisubr word [0x83c1]
+ wait
+ in ax, 0x65
+ sbb ax, 0xaf60
+ mov cl, 0xe0
+ dec dx
+ or [bx+di-0x6d], di
+ daa
+ add al, 0x7c
+ into
+ adc sp, 0x1715
+ adc [di], al
+ jnz 0x1089
+ sbb al, 0x4d
+ dec di
+ or ah, [bp+si]
+ push word 0x3002
+ pop es
+ dec sp
+ dec dx
+ o32 cld
+ sbb [fs:0x8277], bl
+ pop bp
+ push bp
+ retf 0xb295
+ push si
+ lfs dx, [di+0x1c59]
+ or ch, bl
+ mov [bx+si+0x11d4], cl
+ test [bp+si], cx
+ invalid
+ iretw
+ call word 0x5a3:0xafeb
+ inc ax
+ and bx, 0x974a
+ call word 0x9856:0xf431
+ stosb
+ lock stosw
+ push si
+ or ax, 0xa868
+ imul dx, [bx-0x27], 0x4374
+ cmp bl, ah
+ dec dx
+ mov dh, [0x5d17]
+ jle 0x10a3
+ pop bx
+ adc ax, 0xb11f
+ loope 0x108c
+ out dx, ax
+ xchg sp, ax
+ dec cx
+ cmpsw
+ xchg si, ax
+ sub di, bp
+ imul byte [bx+0x85bb]
+ or cl, [bx+di]
+ rcl bx, 1
+ mov si, 0xab26
+ jle 0x113e
+ loopnz 0x10eb
+ jae 0x1180
+ clc
+ out 0x76, al
+ pop ax
+ loop 0x1137
+ mov [0xfdf], al
+ dec bp
+ add al, 0x13
+ dec si
+ mov ch, 0xde
+ retf 0x2df
+ in ax, dx
+ loopnz 0x10ad
+ and dl, [di+0x28]
+ invalid
+ cmp [si], dl
+ test [bp+di+0x612c], cx
+ mul byte [di+0x3bad]
+ adc byte [bp+si], 0xbe
+ dec bx
+ xchg bp, ax
+ push ax
+ int1
+ lodsw
+ jo 0x110b
+ pop si
+ push dx
+ mov al, ah
+ iretw
+ push bp
+ add ax, 0xbe2a
+ adc al, 0x30
+ xchg cx, ax
+ cmp si, [bx+di+0x8]
+ ret 0x6b83
+ mov dh, 0xbe
+ insb
+ arpl [bp+si], cx
+ and [bx], dx
+ clc
+ loope 0x10e3
+ rep cwd
+ pop ds
+ jnp 0x110f
+ sbb ax, 0xc8f1
+ call word 0x9729:0x98b7
+ mov cl, 0x1a
+ call 0xffffffffffffe04c
+ push cx
+ mov [0xf280], ax
+ test [bx+si+0x90fb], bh
+ xchg di, ax
+ push di
+ js 0x117e
+ repne insb
+ rcpps xmm4, xmm7
+ fstp qword [di]
+ inc di
+ invalid
+ add dx, [ecx+0x8a9204f2]
+ das
+ lds dx, [di+0x18]
+ cmp al, 0xce
+ popfw
+ rcr byte [di-0x24], 1
+ jns 0x113f
+ adc sp, [di]
+ call 0xffffffffffffb0a7
+ inc sp
+ mov sp, 0x7652
+ add byte [bx+di+0xc9fd], 0xce
+ invalid
+ push cs
+ mov cx, 0x4d00
+ mov dx, 0xf583
+ sbb ax, 0xb376
+ xor ax, [bp+si+0x5d]
+ push cs
+ pop ss
+ repne rcl word [bx+si], 0x25
+ invalid
+ jb 0x11db
+ test al, 0xb6
+ lodsw
+ loope 0x11f6
+ into
+ jcxz 0x11fb
+ xlatb
+ push sp
+ rol word [bx], 0x91
+ mov cl, [bx+0x7c17]
+ and bh, [si-0x5d]
+ xor ax, 0xb6de
+ dec dx
+ mov di, 0x12f1
+ cld
+ inc cx
+ retf
+ or al, 0xe5
+ and al, 0xe3
+ std
+ mov [si+0xb677], cr0
+ wait
+ lodsb
+ jmp 0xffffffffffffdd90
+ xchg si, ax
+ test al, 0xf6
+ and al, 0xfe
+ out dx, ax
+ dec si
+ pushfw
+ xchg bp, ax
+ xchg si, ax
+ xor cl, [bp+di]
+ adc word [bp+si], 0x1d
+ push 0x1b
+ out dx, ax
+ xor ax, 0x7ae7
+ xlatb
+ jmp word 0x662a:0x8c3
+ salc
+ pop dx
+ jb 0x11da
+ dec bx
+ or bl, bh
+ lahf
+ call 0xfffffffffffffe65
+ jz 0x128a
+ or [bx+si+0x1e], dx
+ in ax, dx
+ jmp 0x1252
+ push word 0x27c4
+ cld
+ inc sp
+ sahf
+ pusha
+ int 0x97
+ aad 0x64
+ int1
+ add ax, 0xf27a
+ mov cx, 0x482d
+ sbb sp, di
+ push ds
+ cmp ax, bp
+ jmp 0x11e8
+ mov al, [0xd4d5]
+ wait
+ mov [di], bx
+ shl cl, 0x15
+ mov dh, 0x2a
+ mov cl, 0x25
+ loop 0x127f
+ push cs
+ and word [bx+di-0x76], 0x8636
+ lahf
+ mov cx, 0x8984
+ inc bx
+ test ax, 0xc7bb
+ xor [bx-0x3d], dl
+ sbb ax, [bx+si]
+ xchg [bp+si], bl
+ mov [0x392e], al
+ or al, 0xab
+ hlt
+ insb
+ inc bx
+ or [si+0x58], bl
+ sahf
+ out dx, al
+ mov [0x324f], ax
+ sub ax, 0x4fe5
+ pop dx
+ mov al, [0x316e]
+ clc
+ stosw
+ test [bp+si], bh
+ shr word [bx], 1
+ fadd st1, st0
+ inc di
+ fidivr word [di-0x2d]
+ pop sp
+ mov cx, ss
+ out dx, ax
+ invalid
+ add al, 0xb6
+ jo 0x1276
+ shr dword [bx+di], 1
+ invalid
+ push bp
+ retf 0x8a07
+ neg byte [bp+0x1678]
+ xor [0xd62e], bp
+ ror word [bx+0x12ae], 1
+ pop ss
+ jge 0x12fc
+ cmp al, 0xd6
+ shr byte [bx+di-0x76], 0xab
+ jae 0x1317
+ adc ax, si
+ mov bl, 0x2a
+ mov al, [0xe9cf]
+ out dx, ax
+ add [si+0x6c], si
+ sbb ah, [bx-0x72]
+ cmpsb
+ mov ax, 0x9209
+ fld qword [bp+di]
+ test [bx+di+0x4], ch
+ shl [bp+di+0x1174], cl
+ mov cl, 0xe7
+ shl byte [si+0x58], 1
+ invalid
+ mov dh, 0x99
+ push si
+ lodsw
+ insb
+ rep int 0xc5
+ imul si, [bp+0xbaf4], 0xd418
+ test ax, 0x3e6a
+ fsub qword [bx+si+0xa367]
+ cmc
+ adc al, 0xda
+ leave
+ sbb [bp+si-0x64], sp
+ cmp ax, 0x46d1
+ jnp 0x132a
+ pop ss
+ xchg bx, ax
+ std
+ out dx, al
+ in al, 0x2d
+ sub [si+0x1ba9], cx
+ in ax, dx
+ push di
+ xor dh, ah
+ retf 0x52a7
+ repne daa
+ clc
+ jp 0x1372
+ pop cx
+ mov ch, 0x16
+ pop di
+ movsw
+ inc sp
+ mov al, [0x6f88]
+ shld [ebp+0x1fd61f], cx, cl
+ stc
+ push ss
+ dec ax
+ ret
+ lds di, [bx+0xbc93]
+ mov al, [0xdd9a]
+ push bp
+ mov al, [0x6932]
+ hlt
+ o32 jl 0x131b
+ int1
+ dec dx
+ jg 0x134d
+ pop bx
+ pop ss
+ cmp al, 0x16
+ and cx, cx
+ push sp
+ into
+ sti
+ mov ax, [0x2e6d]
+ pop di
+ cmp bl, [cs:bp+di]
+ fprem1
+ inc bp
+ a32 outsw
+ pusha
+ inc cx
+ fidivr word [bx+0xfbfd]
+ cmpsw
+ sbb sp, ax
+ pop es
+ in ax, 0x3a
+ push ds
+ imul sp, [di+0xaf9a], 0xb22d
+ js 0x12ed
+ mov ah, 0xf9
+ sbb byte [gs:di+0xf2a0], 0x52
+ xchg sp, ax
+ jmp 0x1314
+ pop dx
+ loopnz 0x1307
+ or [di], ch
+ int1
+ xor [bx], bx
+ leave
+ sbb ax, bp
+ outsb
+ push ss
+ invalid
+ mov bx, 0x3fdb
+ pop dx
+ shl word [bp+di], 1
+ jmp 0x1319
+ cmpsw
+ jmp word 0xf3d0:0x94f7
+ clc
+ imul ax, [si], 0x874e
+ sbb [es:bx+di+0x6f], si
+ pop ax
+ push ds
+ mov fs, [bx+si+0xd55c]
+ salc
+ iretw
+ arpl [bp+si+0x4d], sp
+ mov dl, dh
+ scasw
+ xlatb
+ sub bl, [bx+si+0x2985]
+ aad 0xcd
+ mov ax, [0x5194]
+ adc bx, [bp+si+0x3e65]
+ xor ax, 0xef5f
+ pop es
+ into
+ push ax
+ mov ss, bp
+ insb
+ and byte [si-0x7b], 0xac
+ lahf
+ push sp
+ mov sp, 0xf68
+ xchg bp, ax
+ in ax, 0xa0
+ adc bh, dh
+ invalid
+ lodsw
+ repne jno 0x139c
+ jb 0x13ca
+ xlatb
+ or [bp+di], sp
+ popa
+ jp 0x1370
+ call word far [si+0x96ca]
+ jg 0x140e
+ call word 0xba14:0xebe
+ out 0xe1, al
+ mov dh, cl
+ add dl, bl
+ shl word [bp+si], cl
+ cmp ah, bh
+ adc ax, 0xb335
+ call 0xffffffffffffe44e
+ jmp 0x4a13
+ fst dword [di+0xeb37]
+ dec ax
+ adc ax, 0x1614
+ mov word [0xe96e], 0x9b74
+ mov al, [0x1053]
+ fcom st0, st7
+ mov bp, 0xffe0
+ in al, dx
+ test ax, 0xc923
+ jb 0x13f1
+ invalid
+ cwd
+ scasw
+ push 0xa3
+ movsw
+ jno 0x13fa
+ int1
+ popfw
+ inc bp
+ ret 0x7d8
+ inc dx
+ mov eax, 0x21693b54
+ ret
+ pop bx
+ out dx, al
+ dec cx
+ pop sp
+ and ax, 0xf28a
+ push cs
+ xchg cx, ax
+ dec sp
+ xchg si, ax
+ stc
+ jle 0x143a
+ jmp 0x13c2
+ test [di], bp
+ aam 0x4c
+ das
+ int 0xbe
+ or ah, [bx+di+0x6]
+ test al, 0xd9
+ mov ax, 0x4195
+ and ah, cl
+ xchg dx, ax
+ cmpsw
+ inc sp
+ push si
+ sbb [si], bp
+ mov ax, 0xd9c9
+ sbb byte [di+0x5743], 0xa5
+ mov cx, [bx+0x6389]
+ sub al, 0x58
+ test ax, 0xaebd
+ xlatb
+ and bh, [bx+si-0x2c]
+ sar word [bp+si+0x2cec], 0x33
+ dec di
+ fbstp [bx+si]
+ loope 0x1401
+ inc bp
+ test al, 0x31
+ pushfw
+ dec sp
+ inc dx
+ add [si+0xf433], sp
+ mov dx, 0xfdff
+ jbe 0x13fc
+ cmp di, [bx+di+0x3717]
+ test [di-0x6d], dl
+ enter 0xd9ab, 0xfc
+ rcl byte [di+0x3f], cl
+ adc [bp+si+0xddb3], ax
+ dec di
+ sub word [si], 0x3a
+ mov al, [0x70d2]
+ mov bx, 0x21c6
+ inc dx
+ into
+ jnz 0x14d0
+ pop sp
+ or [bx+di-0x61], ch
+ sub bh, 0xe4
+ out 0xe3, al
+ mov ah, ah
+ cmp cl, bl
+ xchg bp, ax
+ js 0x14e2
+ add ax, 0xbe38
+ jge 0x1508
+ sahf
+ xchg bx, ax
+ loope 0x14dd
+ popfw
+ mov al, [0x6e05]
+ sub [bx+0x3d], di
+ cmp di, [si]
+ cmp bp, [bx+si]
+ sub al, 0xb8
+ inc sp
+ wait
+ xchg bx, ax
+ and [bx+di], si
+ mov cx, 0xbfa3
+ mov cx, 0xb426
+ push cs
+ les ax, [bp+si-0x1f]
+ jle 0x151b
+ movsb
+ lock sbb al, 0x1a
+ jl 0x14ad
+ sub al, 0x21
+ test [bp+di], dl
+ add ax, si
+ insw
+ inc bp
+ cmc
+ xor ax, 0xaf66
+ cmc
+ pop ax
+ enter 0xa7, 0xa9
+ or word [bp+si], 0xba
+ inc si
+ mov bx, 0xf0ca
+ jg 0x14cf
+ jmp word 0x3c69:0x4d5e
+ das
+ rol byte [bx-0xf], cl
+ in ax, 0x77
+ out dx, al
+ and al, 0xf7
+ stosw
+ and [bx+si+0xbaac], ah
+ push fs
+ push si
+ jnz 0x14bc
+ jz 0x1540
+ into
+ inc si
+ mov al, [0x8476]
+ xchg di, ax
+ stc
+ inc di
+ ret 0x77ca
+ adc ax, 0x329d
+ jle 0x1503
+ mov ch, 0xad
+ repne dec si
+ fisub word [bx+di]
+ mov bh, 0x95
+ scasw
+ mov bp, 0x74fa
+ sub sp, sp
+ shl word [cs:bx+si+0x7d], 0xb5
+ bound dx, [bp+si]
+ outsw
+ fsubr st0, st5
+ fcom qword [bx+di-0x57]
+ cbw
+ bound dx, [bp+si+0x7f]
+ push ax
+ dec di
+ cwd
+ pop es
+ inc byte [si]
+ movsb
+ or ah, ch
+ pop ds
+ lea sp, [bp+si]
+ mov si, 0x717f
+ cli
+ and dh, al
+ mov dh, 0x1d
+ jb 0x14ca
+ sub ax, 0x1f1d
+ jb 0x1532
+ out dx, al
+ wait
+ adc al, [bx+di+0x9d2e]
+ adc ax, 0x867e
+ dec ax
+ pop cx
+ dec bp
+ retf 0xd5f8
+ lock mov ah, al
+ lahf
+ mov [0xf5ea], al
+ dec bx
+ cmp [bx+si+0xe645], bp
+ adc dx, bx
+ cmp di, [bx+di]
+ in al, 0x34
+ add [bx+0x1b58], bx
+ sub [si-0x15], bx
+ sub [bx+di], dx
+ mov ax, 0xcca9
+ sub byte [bp+0x5abb], 0x77
+ add word [bx+si+0x36], 0x2251
+ mov bh, 0x1c
+ or bh, [bp+si+0x16]
+ aad 0x60
+ or al, 0x84
+ cmp ax, 0x82ad
+ cmpsw
+ pushfw
+ xchg [bp+si+0x2], cx
+ add [bx+di+0x6ed7], ch
+ mov al, [0x80d]
+ xchg cx, ax
+ retf
+ push dx
+ pop di
+ adc ax, 0x2d27
+ jcxz 0x1620
+ pop sp
+ pop sp
+ push bx
+ arpl [si], bp
+ invalid
+ test ax, 0xb849
+ mov [0xa984], al
+ test ax, 0xd2a8
+ adc dx, bp
+ mov bh, [0xc230]
+ xchg [bp+si], dh
+ o32 mov ah, 0xc3
+ wait
+ add [bp+di-0x4], cl
+ inc bx
+ repne iretw
+ xor dh, [bx+si]
+ outsb
+ mov [bp+di], gs
+ leave
+ add dx, bx
+ inc cx
+ push dx
+ ret
+ sub al, 0x73
+ jz 0x15c4
+ jz 0x15e1
+ imul word [bx+di+0x3607]
+ inc dx
+ invalid
+ pop di
+ std
+ adc ax, 0x70cb
+ mov [0xdca9], ax
+ aas
+ and ah, 0xe2
+ stosw
+ dec di
+ aam 0x42
+ jg 0x15dc
+ movsb
+ test di, sp
+ inc sp
+ adc bh, bl
+ a32 jmp 0x2879
+ sahf
+ aas
+ int3
+ jp 0x1619
+ in ax, 0xad
+ rcr word [bx+0xd60a], 1
+ sar byte [si-0x39], 0xdc
+ cmc
+ adc dx, bp
+ mov al, dl
+ sub bh, [di+0xcb04]
+ xchg [bp+di+0x7919], dl
+ push es
+ adc al, 0xe4
+ pop es
+ mov bl, 0x1e
+ rcr word [bx+si-0x5b], 0x13
+ push es
+ and ax, 0xfe65
+ jg 0x161c
+ push di
+ xchg dx, ax
+ and ax, 0x9b38
+ cwd
+ and ax, ax
+ adc ax, 0x1eca
+ sbb [bx+di], al
+ das
+ cmpsb
+ call word 0xae70:0x22fd
+ or [bp+0x77d6], bh
+ push 0xda
+ xor si, [di-0x33]
+ jno 0x1612
+ hlt
+ clc
+ push ss
+ adc ah, 0xaf
+ popa
+ dec di
+ mov [0xdcaf], al
+ shr word [bp-0x60], 1
+ pop cx
+ mov bx, 0x56ea
+ inc ax
+ cmp bx, bp
+ fnstenv [bp+si+0x8544]
+ jno 0x15f4
+ sbb ax, 0x9a29
+ jp 0x162c
+ lea bp, [bp+si]
+ popfw
+ jno 0x1626
+ in al, 0x9e
+ push si
+ a32 hlt
+ daa
+ mov [0xffe7], al
+ pop si
+ nop
+ xchg bx, ax
+ enter 0x1efc, 0xff
+ aam 0xba
+ loopnz 0x161f
+ jmp 0xffffffffffffed29
+ push word 0x8548
+ in al, dx
+ a32 pop bp
+ cmp ah, [bx+0x30]
+ out 0xe6, al
+ sub ax, [0x7dd6]
+ pop ds
+ dec cx
+ clc
+ adc byte [ds:si-0x1e], 0xe2
+ rep fstp qword [ds:bx]
+ push cx
+ xchg si, ax
+ test al, 0x96
+ stc
+ jz 0x1661
+ mov si, 0xb604
+ iretw
+ dec cx
+ or ax, 0x445e
+ test ax, 0x6a6e
+ ja 0x1695
+ scasb
+ aas
+ xchg di, ax
+ invalid
+ invalid
+ lock das
+ cmp ax, 0x32a8
+ push si
+ into
+ xor [bp+si], dl
+ xchg bp, ax
+ xor al, 0x70
+ mul byte [bp+di]
+ shl word [di+0x13], 0x62
+ scasb
+ lds si, [bx-0x48]
+ outsw
+ xchg dx, ax
+ push bx
+ out 0xd9, al
+ o32 xor bl, [bp+di]
+ int1
+ imul bp, [bp+0x8118], 0x641
+ adc word [si], 0x5f
+ mov bx, 0x152b
+ invalid
+ ret 0x343e
+ or al, 0xcf
+ lahf
+ popa
+ retf 0x474
+ jo 0x168a
+ cmp dl, [di+0x5eb5]
+ wait
+ inc bx
+ int1
+ invalid
+ mov dh, 0x82
+ mov dh, [bx+di+0x1018]
+ cmp [di+0x2490], bh
+ fidiv dword [bx+0x5]
+ mov al, [0x37a2]
+ dec si
+ pop es
+ dec sp
+ enter 0x8c8d, 0x2d
+ xchg [di+0x9e2c], bp
+ test word [bp+0x5e], 0x92d7
+ lahf
+ cmpsw
+ xor di, [si-0x61]
+ xor ax, 0xefb4
+ xchg [bx-0x74], ah
+ pop sp
+ fisub dword [bx+si+0x69a0]
+ jle 0x178f
+ adc [di+0x56], ch
+ jno 0x177c
+ mov sp, 0xd095
+ dec ax
+ loope 0x16fd
+ mov di, 0x805a
+ mov dl, ah
+ mov cx, 0x8344
+ mov ax, [0xa1ba]
+ and al, 0x30
+ jns 0x1738
+ add ax, 0x464
+ jbe 0x1787
+ ret 0xf750
+ mov ax, [di+0x4ef8]
+ xor sp, [bp+si]
+ aaa
+ sbb dx, [bp+si+0x6164]
+ mov [0x5e62], ax
+ retf 0x78ab
+ push si
+ stosb
+ or [bx], bp
+ or ch, [si-0xa]
+ a32 std
+ jae 0x172e
+ test word [bx-0x76], 0x8686
+ adc al, 0x4d
+ sti
+ pop dx
+ fs lodsb
+ cmc
+ add [di], cx
+ dec di
+ outsw
+ lodsw
+ or sp, si
+ adc cx, ax
+ mov bl, ch
+ jmp word 0x3bf3:0x5c6b
+ daa
+ loop 0x1765
+ int1
+ or ax, 0x6a7b
+ cmp si, [bp+si+0x5d]
+ inc cx
+ call 0x6996
+ in ax, 0x61
+ int3
+ sbb dx, [0xa49d]
+ fcom dword [bp+si]
+ rcr word [di+0x55ab], cl
+ push sp
+ in al, 0xf7
+ int 0x9
+ pop dx
+ out 0x9b, al
+ adc [bp+si], ax
+ out dx, al
+ ficom word [di+0x36]
+ imul bp
+ popa
+ mov si, 0x9112
+ sub ax, [bp+si+0x9]
+ ret 0x9e86
+ or cx, [bx+di]
+ jno 0x1819
+ push es
+ outsb
+ jg 0x17f2
+ cmpsw
+ mov sp, 0xb93
+ mov ah, 0x3f
+ cmpsw
+ xchg sp, ax
+ movsb
+ mov sp, 0x464
+ ret
+ invalid
+ inc bx
+ pushfw
+ or al, 0x20
+ mov si, 0x97b2
+ mov [bp+si], gs
+ imul dx, sp, 0xa76e
+ or al, 0xbb
+ js 0x17b6
+ jz 0x17eb
+ dec sp
+ jmp word far [bx+di-0xa]
+ mov ax, [0x7eef]
+ cmp [bx+di+0x7676], sp
+ lahf
+ popfw
+ mov [0xf5c8], ax
+ xor ax, 0xa85b
+ jmp 0xffffffffffffb895
+ test ax, 0x7b3e
+ mov bp, 0xa3c8
+ ja 0x1827
+ test [di+0x2579], cl
+ stosw
+ test [bp+di], cx
+ add bp, [di+0x9129]
+ jmp 0x1795
+ cwd
+ nop
+ imul sp, [di], 0x8c
+ cli
+ pop sp
+ xchg bx, ax
+ invalid
+ insb
+ xor ch, [bx]
+ retf 0xd0d4
+ nop
+ mov si, 0xe28d
+ insw
+ test [bp+0xa663], bx
+ stosw
+ repne pop fs
+ pop ss
+ mov cl, 0x0
+ adc al, 0x6c
+ retf
+ aas
+ push cs
+ inc ax
+ inc bx
+ push 0xe6
+ dec bp
+ jb 0x183d
+ jmp 0x180e
+ sar al, 0xef
+ loopnz 0x17e6
+ or ax, bp
+ int3
+ dec byte [bp+di-0x2d]
+ stosb
+ wait
+ sub [bx+0x922], dl
+ scasb
+ lock xor ax, 0x65e6
+ cmpsw
+ add al, 0x6d
+ pop ax
+ xchg bp, ax
+ pushfw
+ pop bp
+ and ax, 0x81f2
+ ret
+ or ax, 0xf4c1
+ jbe 0x18ba
+ inc dx
+ or [di], cl
+ dec si
+ dec di
+ fldcw word [bx+si+0x3cae]
+ push word 0xaf5c
+ add [di], dh
+ jmp 0x18f0
+ jbe 0x18ef
+ adc [di+0x7402], bl
+ dec dx
+ cmpxchg dh, bl
+ out 0x4d, ax
+ mov bx, [bp+si+0x12fe]
+ pop sp
+ or dh, [bp+di+0x6b]
+ sahf
+ xlatb
+ scasb
+ hlt
+ mov cx, 0x4b74
+ jge 0x18dc
+ out dx, al
+ jns 0x18eb
+ cmc
+ arpl [bx], di
+ sbb ax, 0xec9
+ and ax, 0x9120
+ mov di, 0x76c7
+ mov cl, 0x43
+ iretw
+ pusha
+ aad 0xe6
+ pushfw
+ std
+ pop sp
+ xor al, 0x91
+ push bx
+ shr [bx+si], cl
+ mov [0xbb75], ax
+ pop bx
+ rep jnz 0x18a7
+ or al, [bx+0x33]
+ out 0x27, ax
+ rol ax, cl
+ test [bp+di+0x3f], dl
+ push di
+ and ax, 0xbabb
+ mov dl, 0x32
+ push si
+ out 0x5e, ax
+ jo 0x1932
+ outsw
+ stc
+ push si
+ loop 0x18e2
+ sub [bp+si+0x3d02], ax
+ xlatb
+ in ax, dx
+ and [bx+si+0x1eb9], di
+ or byte [bx-0x6e], 0x2f
+ jp 0x18f2
+ bound si, [di+0x28]
+ rol byte [bp+si+0xe536], 0x53
+ xchg sp, ax
+ dec di
+ jae 0x18e3
+ xchg bx, ax
+ pop di
+ out 0x95, ax
+ aam 0x90
+ ret 0x476e
+ iretw
+ sar word [bp+si+0x9f23], cl
+ dec ax
+ xchg [bp+si+0xb884], ax
+ ret 0xc8a2
+ pop di
+ pop di
+ out dx, al
+ jno 0x18b4
+ and al, 0xa1
+ xchg dx, ax
+ aad 0x93
+ wait
+ jz 0x197a
+ fild dword [bx+di+0x9371]
+ add [si], cl
+ sub cx, [bx+si+0xf270]
+ jns 0x1999
+ mov di, cx
+ invalid
+ mov [bx+si+0x975], cs
+ int3
+ add ax, 0xb9fb
+ jp 0x18b5
+ iretw
+ sbb ax, 0x45df
+ xchg bx, ax
+ dec bp
+ in al, 0xb7
+ clc
+ push ax
+ xor cx, [si]
+ and ax, 0x73a
+ adc [si], al
+ rcl word [bp+si+0xaba6], cl
+ into
+ lodsb
+ pop si
+ jnp 0x19a4
+ push word 0x2ab8
+ inc di
+ adc byte [bx+si], 0xb1
+ mov al, 0x43
+ rcr word [bx+si+0x54], 0x68
+ and ax, [bp+di]
+ xor al, 0x6d
+ out dx, al
+ mov sp, 0x6e32
+ ret
+ add [bp+di], si
+ outsw
+ push cs
+ mov si, 0xf9c7
+ inc dx
+ dec sp
+ xor ax, 0x960
+ xor al, 0xd6
+ push cs
+ pop sp
+ add [si], cx
+ retf
+ cmp ax, 0x191a
+ mov cl, 0x32
+ dec si
+ sbb dl, [bx+si+0xa12c]
+ aaa
+ inc bp
+ cbw
+ mov cx, 0x677a
+ cmp [si], cl
+ cmp [bx+si+0xb9a5], dh
+ cld
+ popa
+ sbb [bp+0x7468], bx
+ and sp, [bp+di+0x423b]
+ dec si
+ jz 0x19f0
+ loop 0x195c
+ cmp bh, [di]
+ and [di+0xf], bx
+ dec ax
+ add cl, [si-0x57]
+ jcxz 0x19b9
+ mov cl, cl
+ mov [si+0x351c], cx
+ scasb
+ jns 0x1981
+ in ax, dx
+ xor [bp+di+0x2f], ch
+ invalid
+ push dx
+ test [bp+0x80d2], bh
+ dec si
+ mov [0xaa6f], al
+ add [fs:si], dl
+ and [bp+si+0xe071], ch
+ arpl [bp+0x57], cx
+ aas
+ mov al, 0xd4
+ sub di, ax
+ retf 0x3e58
+ cmp [bp-0x1e], dx
+ sti
+ outsb
+ xchg sp, ax
+ loope 0x1a4d
+ jp 0x1a3b
+ les bx, [si]
+ invalid
+ invalid
+ retf 0xbf6c
+ mov dh, al
+ mov bx, [di+0x636f]
+ std
+ xor [di+0x32], bl
+ stc
+ mov [bp+si-0x6d], ch
+ xchg cx, ax
+ sti
+ sar word [bx+di+0x40], cl
+ mov bx, 0x9f97
+ jle 0x1a11
+ a32 sti
+ add [0xda5d], al
+ ret 0x72d1
+ int3
+ push dx
+ push di
+ push si
+ push si
+ jmp word near [si+0x6832]
+ or dl, [bx+di]
+ js 0x1a27
+ ret
+ ror byte [bx-0x38], 1
+ shl word [bp+di], cl
+ call word far [si+0xf751]
+ or [si], cl
+ mov si, 0x3c80
+ popfw
+ enter 0x79f9, 0x92
+ dec cx
+ dec si
+ jo 0x1a4f
+ lodsb
+ or al, 0xca
+ jmp word 0x9c7d:0x7faa
+ bound ax, [si+0x434e]
+ inc cx
+ neg word [si-0x15]
+ add al, 0xab
+ mov sp, 0x5c82
+ inc di
+ inc ax
+ insw
+ or [si+0x5cd0], al
+ call word 0x9107:0x62d4
+ pop si
+ nop
+ pop sp
+ cmp [bp+0x6095], ah
+ jmp word 0x91c1:0xdac7
+ pop cx
+ pushfw
+ o32 cmc
+ call 0x6f4b
+ out 0x8c, al
+ inc si
+ dec cx
+ mov bl, 0xc9
+ daa
+ jo 0x1ac9
+ dec bx
+ fcomi st0, st5
+ repne outsb
+ invalid
+ or bh, [bx+si+0x39]
+ sub ah, [bx+si]
+ mov dl, 0xb3
+ sub al, 0x98
+ push dx
+ mov [bx+si+0xe], ah
+ shl [bx+0x866c], cl
+ mov ch, 0x6e
+ inc bp
+ js 0x1aab
+ movsb
+ xchg sp, ax
+ cmp al, 0x46
+ mov ax, [0xd8a4]
+ push word 0x585
+ fdivp st3, st0
+ mov ax, 0x6d4f
+ mov al, 0xa
+ jo 0x1b05
+ xor bx, sp
+ pop ds
+ js 0x1a86
+ nop
+ pushfw
+ jnz 0x1ae9
+ push si
+ retf 0x694b
+ rcl byte [bp+si-0x56], cl
+ out dx, al
+ scasw
+ lds di, [bx+0xe]
+ sahf
+ imul dx, [bx+si+0xe1d1], 0x6dde
+ out dx, al
+ sbb ax, cx
+ mov si, 0x7f18
+ cmp [bp+di-0x60], ax
+ adc cl, [bx+0x984c]
+ dec si
+ wait
+ sub [bx+si-0x48], ax
+ test al, 0x3a
+ add [bp+di+0x7779], si
+ rcr byte [bx+si+0x6e9], cl
+ repne jcxz 0x1ac4
+ mov dx, 0x3c22
+ salc
+ xor [bp+si-0x66], cx
+ adc al, 0x17
+ jz 0x1b23
+ mov bx, 0x989d
+ jns 0x1aa5
+ fmul dword [bx]
+ mov [bp+di-0x35], dx
+ jle 0x1ac1
+ lodsw
+ pop ss
+ iretw
+ mov [bp+si+0x82cd], ch
+ adc ax, 0xb78
+ cmp bh, [0x8483]
+ or ah, cl
+ inc ebp
+ mov dl, 0x4e
+ add dl, [bx+si+0xe565]
+ cld
+ iretw
+ invalid
+ dec di
+ jae 0x1ad4
+ aam 0x6b
+ sbb si, [bp+si+0x5de6]
+ xchg [bp+di+0x1410], bh
+ sbb dh, 0xf1
+ cmp al, 0x91
+ mov dx, [bx+di+0x46]
+ sbb al, 0x68
+ outsb
+ adc al, 0x91
+ mov al, 0x9
+ jmp 0x372a
+ mov dl, 0xf0
+ call word near [bp+si]
+ add ax, 0x8cbb
+ inc sp
+ sbb bx, [bx]
+ mov ch, 0x79
+ out 0xca, ax
+ mov dx, 0x7a67
+ mov al, 0x8a
+ aad 0x51
+ shr di, 0xb7
+ xor [bp+di], dx
+ pop sp
+ mov cr1, ax
+ shl word [bx+di+0xe304], cl
+ dec di
+ xchg [bx+di], ah
+ sbb ax, 0x579
+ push sp
+ pop si
+ out 0xe2, ax
+ xor dh, [bp+0x7a]
+ add al, 0xa3
+ call word 0xfd50:0xe644
+ call word 0xb986:0x2e46
+ std
+ mov di, 0xe023
+ add [di+0x8cdb], ch
+ enter 0x4e13, 0xd9
+ mov cl, 0x89
+ inc cx
+ mov ch, 0x96
+ sbb ah, cl
+ xchg di, ax
+ adc cl, ch
+ in al, 0x61
+ jcxz 0x1b3f
+ movsw
+ mov di, 0x7b96
+ mov dx, 0x950f
+ dec sp
+ and ax, 0xaabd
+ mov di, cx
+ fidivr word [bp+di-0x65]
+ adc [bp+di+0xd52a], cl
+ bound bp, [bx+0xb9ff]
+ js 0x1b68
+ test al, 0x15
+ dec ax
+ sti
+ dec bx
+ stosb
+ or dh, ch
+ fldenv [di]
+ mov cx, 0x448a
+ test [bp+si-0x14], ax
+ add bh, [bp+di+0x4789]
+ pop bx
+ o32 mov [bx], dh
+ mov si, 0x773b
+ pop ds
+ mov [0x1b42], al
+ inc bx
+ cmc
+ aaa
+ into
+ push si
+ cmp ax, 0x84b6
+ mov ah, 0x68
+ pop si
+ cmp al, 0x52
+ sbb bl, [bp+di+0x3a]
+ mov sp, 0x5363
+ salc
+ scasb
+ mov ax, 0xd139
+ arpl [bp-0x4a], bx
+ jmp 0xe40
+ sbb [bx+si], ecx
+ scasw
+ bound ax, [bx+di+0x1095]
+ inc di
+ push di
+ test cl, al
+ cmp bp, ax
+ dec ax
+ hlt
+ repne xchg [si+0x46], bl
+ lodsb
+ or ax, 0xc5e
+ fdiv dword [gs:di-0x17]
+ cmp bl, bh
+ or [bx+di-0x28], cx
+ ret 0xd22c
+ invalid
+ pop di
+ scasb
+ xchg [di+0x7], cx
+ pop ds
+ dec ax
+ movsb
+ ret
+ jl 0x1bde
+ pop dx
+ std
+ mov bp, 0x7bf4
+ dec sp
+ stosw
+ dec di
+ pusha
+ xor al, 0x7a
+ ret 0xf29c
+ invalid
+ sub [bp+0xba93], sp
+ xchg [bp+0x54], sp
+ mov dl, 0xbb
+ fldenv [0xa11c]
+ fstp tword [di+0xd88d]
+ xchg di, ax
+ cmc
+ cmpsw
+ mov al, 0x3f
+ in al, dx
+ cli
+ xchg sp, ax
+ mov di, 0x43cb
+ add ax, 0x5bb3
+ rcr word [bp+di+0x30], 0x67
+ sub dh, [di+0x1d]
+ pop di
+ test [bp+di+0x6e], ch
+ inc sp
+ xchg [bp+di+0xa8b5], sp
+ jp 0x1ca9
+ salc
+ and byte [bx+di+0x56eb], 0x31
+ jo 0x1c01
+ sbb ch, [di]
+ or al, 0x86
+ push ss
+ cmp [bx+si-0x1d], dx
+ mov es, [bp+si+0xccdb]
+ retf
+ and ax, 0x3136
+ mov al, [0xcfd0]
+ xchg di, ax
+ sub al, 0xf5
+ dec cx
+ loop 0x1c87
+ loopnz 0x1c57
+ jnp 0x1c40
+ invalid
+ neg word [si+0x4ba3]
+ inc cx
+ insw
+ adc ax, 0xd690
+ loopnz 0x1bfc
+ movsb
+ das
+ pop bp
+ out 0x5c, ax
+ push cs
+ invalid
+ push di
+ adc di, dx
+ sbb ax, [di+0x3704]
+ xor cx, [di+0x8e2e]
+ ret 0x30cd
+ outsw
+ mov ax, [0x89de]
+ in al, 0x6d
+ loope 0x1cc0
+ push cs
+ jnz 0x1c64
+ pop ds
+ jge 0x1c94
+ add ax, 0xa2e6
+ fild dword [bp+di]
+ cmp dh, ch
+ dec ax
+ mov di, 0xf79
+ leave
+ arpl [di+0x5d], bp
+ jo 0x1d23
+ nop [bx+0x65]
+ jz 0x1cdc
+ adc cl, ah
+ aaa
+ pop ds
+ mov [0xab26], al
+ mov ah, 0xd7
+ xchg bx, ax
+ iretw
+ salc
+ sbb [bx], di
+ inc di
+ in al, 0x2c
+ pop cx
+ pop bx
+ rep insw
+ scasw
+ add byte [0x7bd], 0xb7
+ leave
+ invalid
+ cwd
+ xlatb
+ out dx, ax
+ retf
+ and al, 0x70
+ push bp
+ push cs
+ pop di
+ cmp ax, 0x7e82
+ xchg cx, ax
+ or sp, bx
+ retf
+ in al, 0x3a
+ jno 0x1d19
+ cmp [bx+di-0x47], bh
+ in al, 0x35
+ mov ax, 0xb9bd
+ push dx
+ push sp
+ jo 0x1d1e
+ dec ax
+ mov ah, 0x89
+ rol word [bx+si-0x65], cl
+ in ax, 0x2d
+ mov ah, 0x36
+ invalid
+ sti
+ push dx
+ invalid
+ lodsb
+ or al, 0x9d
+ mov ax, 0xfc4d
+ or dx, [bx]
+ sbb dl, [bx+0xa637]
+ int1
+ mov bl, 0x34
+ mov bp, cx
+ xor ax, 0xe79e
+ and word [bp+si-0x10], 0x91fb
+ retf
+ invalid
+ jmp 0x10ae
+ in al, 0xdb
+ push cx
+ dec bx
+ jno 0x1cd3
+ fldcw word [bp+0xc7bf]
+ rcl byte [bp+si], cl
+ bswap ax
+ mov di, 0x4899
+ xor ax, 0xd4d7
+ mov di, 0x1f98
+ mov al, 0x5b
+ pop ds
+ ror byte [0x9ed], 0xf3
+ fdivr dword [bx+0x25]
+ xchg [si-0x3f], al
+ mov cx, 0xd29
+ jg 0x1dbd
+ fdivp st4, st0
+ jae 0x1d67
+ jae 0x1d5c
+ wait
+ cmpsw
+ daa
+ mov dx, 0xe596
+ mov sp, 0x7e8d
+ sub ax, 0xcf64
+ std
+ lodsb
+ sbb [bp+si+0xc62b], bp
+ insb
+ and ch, al
+ pushfw
+ jmp 0x1d3e
+ push es
+ pop es
+ mov di, 0x3871
+ int 0x82
+ mov dx, 0x9fa6
+ dec di
+ mov dl, 0x81
+ lahf
+ jnz 0x1cff
+ jp 0x1dbb
+ dec bx
+ mov bx, 0x7f3d
+ lea si, [bp+di+0xb]
+ sub al, 0x7b
+ o32 ja 0x1dc3
+ sar di, 0xf
+ cwd
+ cbw
+ mov ax, [0xb6c]
+ insb
+ ja 0x1d4b
+ cmpsw
+ add cl, [bx+di+0x7e]
+ push sp
+ mov ch, [bx+si]
+ and dx, si
+ scasb
+ fcom2 st7
+ fstp qword [si]
+ shr byte [si+0x7554], 1
+ invalid
+ wait
+ adc ch, [bp+di+0x937d]
+ aad 0x56
+ test ax, 0x3fe4
+ jno 0x1e09
+ loopnz 0x1d6b
+ xor ax, [di+0x7a5e]
+ std
+ jb 0x1da9
+ add ax, 0xfde4
+ into
+ a32 mov ax, 0x7ca
+ pushfw
+ cmp al, 0xc4
+ fisttp qword [bx+di-0x3d]
+ and bl, al
+ mov bx, gs
+ xor [bx], si
+ push ss
+ push cx
+ cwd
+ mov dl, 0x83
+ int1
+ ret 0xb54
+ out dx, al
+ cmp al, 0x92
+ xchg si, ax
+ sbb dh, cl
+ mov bx, [bp+si-0x49]
+ pop es
+ xlatb
+ lodsb
+ imul bp, [bx+si+0x32b], 0x94
+ movsw
+ sbb [bx+si+0xe0f1], dl
+ push es
+ dec di
+ mov cl, 0x1a
+ mov ch, al
+ jae 0x1df6
+ inc sp
+ push di
+ sub al, 0xe4
+ or ah, bl
+ xchg bx, ax
+ pop ds
+ fsub qword [bp+si-0x46]
+ out 0xd4, al
+ xor al, ah
+ int3
+ jp 0x1e4e
+ and cx, si
+ call 0x1af7
+ adc dh, [bx+di]
+ pop dx
+ outsw
+ pop es
+ or [bx+si+0x5f86], dx
+ mov ah, 0x4
+ cmp [bp+di-0x13], al
+ ja 0x1e05
+ pop sp
+ jbe 0x1e31
+ jge 0x1e1a
+ enter 0x1445, 0xe4
+ les di, [si-0x5a]
+ pop si
+ nop
+ jle 0x1e76
+ aaa
+ ja 0x1ea5
+ ja 0x1e29
+ or [bp+di], cx
+ pop ss
+ movsw
+ xor dl, al
+ add byte [bx], 0x83
+ repne jmp 0x1dc9
+ jmp 0x2047
+ pop bp
+ loop 0x1dd4
+ push dx
+ and ax, 0xfeb2
+ pop si
+ int1
+ test bp, di
+ jmp 0x1e47
+ movsw
+ mov di, 0x210b
+ retf
+ cmp dh, [bx+si-0x16]
+ mov ah, 0x1d
+ and [si+0x10], bh
+ aaa
+ out dx, al
+ invalid
--- /dev/null
+ mov edi, 0x95804fae
+ int1
+ cli
+ inc ebx
+ lea eax, [eax]
+ or al, 0xeb
+ aaa
+ add eax, 0xcfca3a9d
+ xor eax, 0xfca13235
+ add dword [gs:eax], 0xf8
+ out dx, eax
+ jmp dword 0x60c2:0x78636e11
+ outsb
+ mov cr1, [ecx-0x6e]
+ jnp 0xffffffffffffffac
+ xchg esi, eax
+ push es
+ lahf
+ add bl, ch
+ out 0x9f, al
+ sar dword [ecx-0x61], 1
+ jmp dword 0xf060:0x85e33f60
+ jl 0x81
+ mov ecx, 0xc0d32522
+ out 0x70, eax
+ push esi
+ pop ss
+ aaa
+ in al, dx
+ xchg ecx, eax
+ and ebp, esi
+ push ecx
+ mov cl, 0xc8
+ sbb al, 0x78
+ into
+ shr ebp, 1
+ adc bh, [ecx+0x7b]
+ pop dword [eax-0x1]
+ jb 0x3e
+ xlatb
+ bound eax, [ebx+0x99f7d184]
+ hlt
+ insd
+ xchg edi, eax
+ mov gs, [esi]
+ loope 0x71
+ mov al, 0x96
+ adc [ebx+0x926c585e], ah
+ ret 0x7e85
+ add ch, ch
+ pop ss
+ daa
+ xchg esi, eax
+ mov bl, 0xe4
+ mov cr0, [ecx+0xfdaf1807]
+ inc byte [ebx+ebp*4]
+ sbb dword [esi+ecx*2], 0x9c886f44
+ push edi
+ mov ecx, 0xd409a448
+ adc al, 0xe9
+ insd
+ sub cl, bl
+ invalid
+ cmc
+ bound eax, [eax]
+ pop ds
+ pop ecx
+ mov [edi], ch
+ xchg edx, eax
+ salc
+ and [ecx], esp
+ push ebx
+ jbe 0xde
+ mov [ecx], edi
+ sar cl, cl
+ add [ebx+0x5e], cl
+ inc ebp
+ iretd
+ daa
+ mov gs, [edx]
+ adc eax, 0x1107e2e1
+ push eax
+ dec ebx
+ repne gs movsb
+ scasb
+ a16 inc esp
+ jae 0x130
+ ret
+ cmp eax, 0x5fe11475
+ stosd
+ insd
+ xor [esp+0x69f80098], esi
+ xor eax, ebp
+ int3
+ push 0xc8
+ cmp esi, [edi+0x9bc32958]
+ daa
+ xor al, [eax+0xa151c8bf]
+ mov [0x705fa0e8], eax
+ in eax, dx
+ add esi, ebx
+ xchg ebx, eax
+ xor byte [ecx+0x4f], 0x37
+ ja 0xa6
+ xlatb
+ o16 shl [eax], cl
+ mov bh, 0x91
+ push ebp
+ push esi
+ nop
+ push esp
+ mov bl, 0x83
+ invalid
+ pop ecx
+ mov ebx, 0xcf58c4e3
+ mov ecx, [eax+0x20]
+ jbe 0x145
+ dec bp
+ js 0x94
+ xor ch, [eax-0x65]
+ sahf
+ dec ecx
+ or bh, [esi+0xdbc2dd9a]
+ and eax, 0x8134fcda
+ xchg [edx], bh
+ mov al, 0xd0
+ xchg esp, eax
+ push ss
+ sub eax, 0xe7fb27a4
+ cmc
+ and eax, 0x7f5f47f6
+ jno 0x198
+ and dword [esi-0x79], 0x84d0c980
+ cdq
+ div word [edi-0x44]
+ sub bl, ch
+ push esp
+ or [ecx+0xadd39a4a], dl
+ jnp 0xea
+ movsd
+ sub al, 0xe0
+ wait
+ push ss
+ invalid
+ test al, 0x7b
+ int3
+ cmpsd
+ in al, 0xac
+ mov dl, 0xd8
+ push esp
+ add edi, ecx
+ salc
+ push ss
+ bswap ebp
+ sbb eax, 0x132463c4
+ sub [ecx+0x98b4a3f5], al
+ fstp8 st1
+ or al, 0x40
+ out dx, eax
+ or [ecx-0x47], esp
+ jae 0x162
+ call 0xffffffff95858333
+ invalid
+ ficom dword [ecx]
+ movsb
+ jmp dword 0x5268:0x323578b0
+ invalid
+ or [eax+0xe68fd1ef], cl
+ xchg ecx, eax
+ jns 0x112
+ pushfd
+ jb 0x1cd
+ ficom word [esi]
+ push cs
+ das
+ loopnz 0x14f
+ push eax
+ xor [eax+0x2f], esp
+ cli
+ insd
+ les esi, [ebp+ebp+0x69]
+ outsb
+ add esi, [edi]
+ jz 0x170
+ dec esp
+ fbstp [eax]
+ ret 0x7e91
+ xor eax, 0x9d1189e
+ xchg edi, eax
+ sub eax, 0xe34fb563
+ adc dword [edx+0x50], 0xbe
+ mov fs, [esi]
+ sbb eax, 0x8507dfba
+ pop esi
+ xchg [fs:edi+0x772f0d6d], esi
+ movsb
+ push cs
+ pop ebx
+ add [ebx+0xc3d44faf], edx
+ add ebp, [esi]
+ xor esi, [ebx+edx*8-0x73]
+ xlatb
+ mov esp, 0x84e415b
+ push cs
+ iretd
+ and esi, [ebx+0x42]
+ int3
+ push esi
+ sbb esp, [edi]
+ jnz 0x222
+ mov edx, 0x27656695
+ xor dl, dl
+ outsb
+ shl dl, 1
+ pop ebp
+ aad 0x47
+ sub [esi-0x9], eax
+ call 0x2d044abe
+ ret 0xd5d9
+ loopnz 0x193
+ xchg ebx, eax
+ or edx, [edx]
+ cld
+ jp 0x227
+ inc edi
+ and ch, bl
+ pop ss
+ retf
+ xchg ebp, eax
+ in eax, 0xf1
+ rep pushad
+ scasb
+ inc ecx
+ push ss
+ pushad
+ mov eax, [0x4f574d9e]
+ mov esi, 0xacddd71e
+ xor al, 0xa3
+ xchg esp, eax
+ shl dword [ebp+0xb39ccece], 0x48
+ pushad
+ test al, 0xdd
+ mov edi, 0x4ebbc7d3
+ inc ecx
+ movsb
+ or al, 0x7c
+ stosd
+ push ecx
+ jnp 0x22d
+ xor bl, [ecx+0x879355b3]
+ ror byte [edx-0x4f], 0xf2
+ xchg ebp, eax
+ lock push ebx
+ xchg ecx, eax
+ push ebp
+ les ecx, [0xbcf5e5cb]
+ ror dl, cl
+ mov al, [0xc81304ba]
+ fucomi st0, st1
+ jge 0x234
+ adc edi, esp
+ std
+ xor [esi], edi
+ out 0x9b, al
+ invalid
+ inc esp
+ xor eax, 0x730c4733
+ jle 0x1f9
+ push eax
+ mov [0x5fa687e4], al
+ sti
+ push dword 0xf234b144
+ mov [0x3d8ab4c3], eax
+ inc eax
+ mov ch, 0x87
+ add ah, dl
+ invalid
+ clc
+ lodsd
+ sahf
+ loopnz 0x2e6
+ pop ebp
+ mov [0x4a3a6118], eax
+ ret
+ sub dl, [esi-0x41]
+ xchg edx, eax
+ mov eax, [0xd9662e8f]
+ div dword [ebx+0xd0f4b5f0]
+ push esp
+ clc
+ shl dword [eax+esi+0x6f], 0xd5
+ lahf
+ push ebx
+ mov byte [edi+0x8ed27cb8], 0xac
+ retf 0xe411
+ sbb [ebp+edx*8+0xebed1caa], bl
+ mov [0xbc346bfc], eax
+ or [edx+0x1e5d8f31], cl
+ add [0x22efb4e4], edx
+ or cl, [esi]
+ push esp
+ arpl [0xd4b9c216], dx
+ sar [ecx+0x7d], cl
+ retf
+ invalid
+ mov ebx, 0x93818ee4
+ inc esp
+ jg 0x2c9
+ loope 0x34f
+ shr dl, 0x87
+ invalid
+ xchg ecx, eax
+ adc [edi-0x4a], dl
+ scasd
+ push dword [edi+0x9d3c946f]
+ scasd
+ in al, 0x1b
+ push edi
+ fdiv qword [ecx+0x5f]
+ jae 0x2b6
+ jg 0x297
+ repne sub byte [bx+di+0x25], 0x7c
+ wait
+ sub dword [ebx], 0xfe1c3c3d
+ mov ch, 0xec
+ cmpsd
+ jp 0x299
+ inc edx
+ invalid
+ push edi
+ xor [edx+ecx*2+0x498841f], edi
+ mov ebp, 0xf0b2a7ed
+ jnp 0x35a
+ sbb [edi-0x44], ecx
+ loope 0x392
+ add [ebp+0xf01581d9], ecx
+ movsb
+ hlt
+ movsb
+ into
+ sbb al, 0x2d
+ cmpsb
+ cwde
+ dec edx
+ insd
+ invalid
+ mov [0x54c7e06f], eax
+ sbb eax, edi
+ cmp eax, 0xbf545531
+ xchg edi, eax
+ push edi
+ js 0x381
+ jge 0x30e
+ dec eax
+ fnstsw word [ecx-0x7f]
+ pop ds
+ shl dword [ecx], 0xe0
+ or esp, [edi+0xd4d52926]
+ push edi
+ arpl [edi+0x38ed8291], bx
+ in eax, dx
+ dec edi
+ neg dword [0x1d58c367]
+ stc
+ insd
+ mov cl, 0x34
+ mov dl, 0x1b
+ mov eax, [0xc33a1f8]
+ mov ebx, 0xd635867c
+ mov [ebx], al
+ inc esp
+ push es
+ out dx, al
+ lodsd
+ pop ss
+ jnz 0x3b5
+ arpl di, ax
+ cmpsd
+ hlt
+ mov edi, 0x95ac2357
+ push ebp
+ inc ebx
+ pop ebx
+ adc eax, 0x8ba88bc4
+ shr eax, cl
+ dec ebx
+ div byte [ecx]
+ bound ebx, [ecx-0x21]
+ fdivr dword [ebp+0xa44b1a13]
+ xor esi, [esi-0x27]
+ sbb [esi], edx
+ ror byte [ecx+0xbb3ebc22], cl
+ outsd
+ and edi, [esi+0xd535f435]
+ scasd
+ add [eax], dh
+ js 0x3dc
+ jmp dword 0x23c5:0xbfdf8522
+ jge 0x3d9
+ xchg edi, eax
+ test [ecx+0x36], bl
+ xor eax, 0x2ef2dd51
+ mov esi, 0x6cdd5b1f
+ push eax
+ fstp qword [eax+0x7a564f77]
+ movsb
+ mov esp, 0x6edc8fdc
+ xor eax, 0x57e4a5d1
+ mov edi, 0x4890a0bc
+ fdivr st0, st2
+ popfd
+ jo 0x39f
+ daa
+ nop
+ in eax, 0xe
+ in eax, 0xc1
+ cmp [ebp+ebx*2+0x1e18e69a], ah
+ xchg [ebx+0x514c44bd], ecx
+ pushad
+ cmpsd
+ outsd
+ inc ebx
+ stosd
+ wait
+ invalid
+ mov eax, 0xe426f49a
+ mov esi, 0x3d7db05c
+ and [ebx+0x34], esi
+ fisubr dword [ecx+0x9]
+ stosb
+ cmp [edi+0xa09cb89c], cl
+ jg 0x44a
+ cmp [esi+0x55f9b487], dh
+ fild qword [edi+0x31]
+ pop eax
+ invalid
+ mov cl, 0x1f
+ clc
+ jns 0x442
+ mov ebp, [edx]
+ in eax, 0x6
+ mov ah, 0x85
+ adc ecx, [ebx-0x1d]
+ inc edi
+ jnp 0x3ed
+ xchg esp, eax
+ invalid
+ jg 0x491
+ bound edx, [ecx+edx]
+ fidiv word [ebp+0x4b4154c3]
+ jle 0x3db
+ test [ebp+0x72685122], eax
+ not byte [edx+0x50]
+ mov [0xab3ad9be], al
+ jo 0x459
+ jmp 0x36460a50
+ add al, 0x6f
+ mov [0xb9c99ce8], eax
+ lodsd
+ jmp 0x4ec
+ sbb eax, 0xac9bb1d1
+ or eax, 0x2af1158e
+ fild qword [ebp+0xc1885224]
+ push edx
+ and eax, 0xf6050662
+ in al, dx
+ push esi
+ jmp 0x4f3
+ push ebx
+ cld
+ or al, 0xe4
+ jnz 0x4bd
+ shl byte [eax], 1
+ mov ecx, 0x10a2583c
+ mov esp, 0x8c1432da
+ jp 0x4af
+ popad
+ inc esi
+ jmp dword far [ebx+0xf6eb2715]
+ int 0xbb
+ dec edi
+ outsd
+ mov dl, 0x55
+ sbb al, 0xbb
+ xchg esp, eax
+ sbb eax, 0x6752a77e
+ and eax, 0xd7a1d401
+ test eax, 0xcacf5092
+ sar dword [esi+0x887acef0], 0xce
+ mov bh, 0xf7
+ and al, 0x80
+ cmp [eax+edx*4], dh
+ in eax, 0xcf
+ xor [esi], ch
+ scasd
+ cmp eax, 0x2b823c89
+ mov [eax], dh
+ mov esi, 0x59a0f5b9
+ jle 0x47f
+ hlt
+ aaa
+ movsb
+ lea esi, [ebx+0x33428281]
+ pop ds
+ mov esp, 0x777cb8f
+ wait
+ repne push esi
+ adc al, 0xb7
+ inc ecx
+ inc ebx
+ dec esi
+ wait
+ cmp eax, 0x8468a78a
+ fstp qword [edx+0x97e93040]
+ aam 0x7
+ mov [0x2d7023a1], eax
+ retf
+ sbb edi, [eax+0xffbc49d3]
+ lahf
+ mov bh, 0x3a
+ pushfd
+ cmpsd
+ mov ah, 0xad
+ or dh, [edx]
+ push ss
+ inc edx
+ xor [ecx], ecx
+ mov edi, 0xa1440147
+ cmp [ebx-0x1d], eax
+ mov dword [esp+esi*4-0x70], 0xb08aa420
+ xchg ebp, eax
+ sbb ebp, ebx
+ mov bl, 0x42
+ xchg [ebp-0x1f], edi
+ xor eax, 0x23062d90
+ lock add bl, [ebx+0x2]
+ popfd
+ leave
+ sar dword [ecx-0x61], 0x7d
+ jp 0x4f2
+ xchg ebx, eax
+ mov ecx, 0x76700e5d
+ fsub dword [eax+0x38de11eb]
+ scasd
+ stc
+ xchg esi, eax
+ mov al, [0x4efd36a2]
+ sti
+ invalid
+ xor al, 0xe7
+ test byte [0x28f76ccd], 0x4c
+ push ss
+ rep inc esi
+ cmpsd
+ leave
+ pop edi
+ jecxz 0x52d
+ retf 0x3450
+ mov ch, ah
+ movsd
+ stosb
+ sti
+ or bl, [ebx+0x1ea54199]
+ mov al, [0x383cc0d6]
+ xchg ebx, eax
+ dec ebp
+ dec edi
+ dec edx
+ dec edx
+ add [eax], ecx
+ adc al, 0x6e
+ inc eax
+ leave
+ adc al, 0x26
+ jmp 0x556
+ invalid
+ insd
+ pushad
+ bound esp, [edi+eax*8]
+ sub al, 0x77
+ or al, 0xae
+ xchg esp, eax
+ invalid
+ repne inc edi
+ dec ebp
+ cmp eax, 0x787cbcd0
+ cmp dh, bh
+ or edx, esi
+ jo 0x55b
+ xor al, 0x9b
+ test byte [ebp+0xbd740164], 0xe9
+ mov [0xd2e9e77a], eax
+ push edx
+ rep push edx
+ mov al, 0x77
+ mov cl, 0xda
+ mov dl, 0xec
+ insd
+ scasb
+ xchg ecx, eax
+ rol bh, 1
+ and eax, 0x47c6ad88
+ cli
+ out 0x66, eax
+ ja 0x5f0
+ mov [0xd24da31c], al
+ jle 0x56f
+ push es
+ jae 0x5f5
+ ja 0x623
+ adc ebx, ecx
+ xchg ebx, eax
+ xlatb
+ cdq
+ pop ds
+ sahf
+ mov ebx, 0xff345910
+ mov al, [0x5ec8f4c1]
+ pop ds
+ cmpsb
+ call 0x793f2d85
+ mov dh, 0xb3
+ jp 0x619
+ lock jmp dword 0xce14:0x103b24f4
+ inc ecx
+ rep fstp qword [eax+0x23]
+ out dx, ax
+ jno 0x59b
+ imul esp, ebp, 0xfd
+ or [ebp+0xae445ba2], ah
+ jecxz 0x5d4
+ cmp bh, ah
+ in eax, dx
+ aas
+ nop
+ sbb al, 0xd8
+ call dword 0x43b6:0x79d8c271
+ inc edi
+ inc esp
+ popfd
+ das
+ pop edi
+ in al, 0xa8
+ xchg ebx, eax
+ mov dh, 0x9f
+ invalid
+ out dx, eax
+ nop
+ test eax, 0x6ed9741d
+ mov eax, [0x53344910]
+ test esi, 0xef612761
+ adc ebx, [edx+0xf2d948a9]
+ sub al, 0x46
+ mov eax, 0x83fec441
+ mov cl, 0x9d
+ scasd
+ cmp esi, eax
+ sub [edi-0x66], eax
+ dec ebp
+ cmp bl, 0x61
+ mov al, [0x25e6ebf3]
+ inc ecx
+ pushad
+ movsd
+ int3
+ test al, 0xc0
+ mov cl, 0x39
+ insd
+ jmp 0x627
+ add eax, 0xda66295d
+ cmp [edi+0x22], edi
+ push eax
+ sub al, 0x5e
+ sbb ecx, [eax]
+ xchg ecx, eax
+ dec ebp
+ out 0xe2, eax
+ pop ebx
+ jp 0x653
+ jmp dword 0x2c79:0xfa79aa3b
+ shl byte [edx+0xb966e325], 1
+ in al, dx
+ lodsd
+ insb
+ add eax, 0x4e2eb90b
+ cmp al, 0xfb
+ sub eax, 0x52f2a8d8
+ mov ecx, [esi+0x8]
+ and ecx, [eax+0xb9f8f452]
+ fcom st0, st7
+ int1
+ mov esi, 0x700d5708
+ mov ebp, 0x678e58a1
+ adc esp, [ecx]
+ adc dword [eax], 0xbf
+ and dword [esp+edx*4], 0xc6
+ push ebx
+ sub eax, 0x9e1fa2af
+ mov ecx, 0xdcdf29ae
+ clc
+ cmp cl, cl
+ cmc
+ enter 0x4f3f, 0xf8
+ adc byte [edx+0xeb4b8e71], 0xb6
+ loop 0x6ad
+ jz 0x66e
+ aam 0x1b
+ push ebx
+ call 0x6e843206
+ bound ebp, [eax+0xabbcc870]
+ sbb ah, bh
+ aam 0xa
+ or eax, 0x1b1a3f6c
+ in eax, 0x7c
+ sbb eax, 0xb9b94d07
+ insd
+ mov bl, 0x8a
+ push 0xf9
+ sbb ecx, [eax+0x1b31669e]
+ mov esi, 0xd1de5b3d
+ js 0x6fc
+ sbb eax, 0x6ffe0d5
+ jge 0x6c6
+ insb
+ inc ebp
+ ret 0xda6
+ mov esp, 0x39e9ba3b
+ xchg ecx, eax
+ jle 0x793
+ mov edx, 0x840bd8e3
+ mov dh, 0xd1
+ les esi, [edx]
+ test al, cl
+ int1
+ fld qword [0x7ec311fa]
+ o16 jae 0x758
+ pop esi
+ das
+ hlt
+ jbe 0x731
+ jge 0x78e
+ ret
+ in al, dx
+ lodsd
+ ja 0x74e
+ pop ebx
+ scasd
+ cld
+ mov bh, 0xa0
+ adc ah, [eax]
+ sbb al, 0x53
+ imul eax, [ecx+0x9b0e938a], 0x53744fdc
+ cmpsb
+ xchg [edx+0x64915082], ebp
+ inc ebx
+ imul byte [edx-0x5d]
+ lahf
+ add eax, 0x6086adde
+ or al, 0xfb
+ or eax, 0xa0926d7b
+ in eax, dx
+ in al, 0x36
+ jbe 0x73d
+ int1
+ xlatb
+ fidiv dword [esi]
+ mov [edi], dl
+ inc al
+ mov [ecx+0x98476253], esp
+ xlatb
+ mov edx, 0x54abea50
+ jo 0x7ae
+ add dh, [edi]
+ fsub qword [ecx]
+ xor [edi+ecx+0x48], ebp
+ lahf
+ arpl [edx-0x4b], bp
+ invalid
+ clc
+ mov esp, 0x9cbba834
+ std
+ jecxz 0x7a0
+ dec edi
+ add ebp, [edi-0x40]
+ mov edx, 0x9717a522
+ sub [esp+edi*4], ch
+ lahf
+ mov esp, 0x47e94f18
+ xchg [ds:esi], esi
+ pushfd
+ push ebp
+ cmp edx, [edi]
+ jz 0x834
+ xchg esp, eax
+ dec ecx
+ salc
+ push ecx
+ aad 0xf9
+ inc byte [edx+0x53fc8bf5]
+ sbb ah, [esi+0xe069e65]
+ shr edx, cl
+ in al, dx
+ pop ss
+ xchg esp, eax
+ and [edx], ecx
+ dec ecx
+ wait
+ daa
+ jle 0x779
+ push ds
+ mov [ecx-0x65], ah
+ inc eax
+ pop es
+ jnp 0x7f4
+ jmp 0x731edc27
+ jns 0x796
+ mov cl, 0xba
+ xor eax, 0x5713d376
+ jp 0x87b
+ cmp eax, [eax-0x2a]
+ xor dword [edi], 0xbe56b7cd
+ jns 0x80f
+ xchg edi, eax
+ in al, dx
+ ret 0xfc88
+ xchg esp, eax
+ outsd
+ mov ecx, 0xcb629fe0
+ outsd
+ popfd
+ inc edx
+ push esp
+ xchg ecx, eax
+ mov ecx, 0x3ff2b740
+ adc eax, 0xb4cf7f6a
+ arpl [esi+0xbbbd507b], bx
+ call dword far [edi+0x63a461e9]
+ mov eax, [ebp+0x4d]
+ push esi
+ pushad
+ or eax, [ebp-0x14]
+ push esi
+ sbb eax, 0x3e8fc0ae
+ dec eax
+ and al, [edi-0x3b]
+ push ecx
+ aaa
+ xchg [ecx+0x6b], esp
+ fcmove st0, st4
+ jmp dword 0x2823:0x34ff9395
+ adc al, bh
+ xor eax, 0xdc2ee2
+ add [ebx+0x55fcd786], eax
+ jg 0x88e
+ jmp 0xffffffff88ddccf9
+ pop ebp
+ cld
+ in al, dx
+ and ecx, [esi+0xf314f6fd]
+ xor [esi+0x8], al
+ fstp qword [eax-0x6e]
+ ja 0x803
+ add byte [eax+0x6bef8a1f], 0x97
+ outsb
+ adc [ebp-0x4b], ch
+ pop ecx
+ sub esi, [0x2d7ff4e5]
+ stc
+ mov [ebx], ds
+ or dword [esp+ebx*8], 0x63ee6442
+ push es
+ push eax
+ das
+ fsubrp st5, st0
+ jl 0x909
+ loop 0x832
+ mov esp, 0x34beb4a6
+ adc eax, 0xc6745838
+ out 0x71, al
+ cmp ch, dl
+ sub ecx, [edx+0x5c519127]
+ sbb [edi+0x33ca5cc1], ecx
+ salc
+ or eax, [edx+0x0]
+ das
+ movsd
+ cmc
+ cmpsb
+ add [ebx+eax*4+0x11], ch
+ jz 0x848
+ and [ebp-0x2d], ebp
+ dec eax
+ retf
+ sbb [ecx], dl
+ mov dh, 0x35
+ rcl dword [edi-0x1f], cl
+ or [eax-0x38], dh
+ pop ds
+ and [eax-0x2f], edi
+ mov cl, 0xc8
+ jecxz 0x951
+ and eax, 0xe26682e6
+ sub al, dh
+ sub bh, [eax]
+ push ss
+ sbb dl, [edx+0xf55550d3]
+ jbe 0x93a
+ leave
+ adc edx, [ebx]
+ mov cl, 0xbb
+ push ebx
+ and eax, [eax+0xa]
+ iretd
+ outsd
+ xor [esi+0x10f4d0e8], edx
+ cmp eax, 0x1cf5d799
+ lds eax, [eax-0x1e]
+ repne jbe 0x937
+ dec edi
+ and ebp, ebx
+ sbb al, [eax+0x2f880b12]
+ pop edi
+ nop
+ xchg esp, eax
+ sti
+ invalid
+ arpl [ecx+0x31da1f77], sp
+ mov al, [0xbdb8071b]
+ call dword 0x2d5a:0xe58d87b
+ pop esp
+ aas
+ pop ss
+ fcmove st0, st3
+ and eax, 0x71674aa9
+ mov eax, [0x310bed12]
+ xor bl, [ebp+edi*8-0x65]
+ aaa
+ xlatb
+ inc eax
+ sub [eax], bh
+ jnz 0x8d3
+ jmp dword 0xa9fe:0xf1be2348
+ movsb
+ or ebx, [ss:eax+0x2d]
+ adc ebp, ebx
+ adc [esi+0x951fd235], ecx
+ mov [esi+0x3f], eax
+ ja 0x957
+ sub esp, edx
+ xor dword [edi], 0xa7
+ loop 0x936
+ std
+ mov bh, [ecx+0x46b49152]
+ in al, dx
+ mov dl, 0x45
+ xchg edx, eax
+ push 0xc5
+ wait
+ pushfd
+ sti
+ in al, dx
+ jge 0x901
+ jbe 0x9be
+ xchg edx, eax
+ inc edi
+ xchg edx, eax
+ cmp ch, cl
+ loop 0x9d3
+ dec ecx
+ lodsd
+ pop ebx
+ xchg [edi+0xab489360], ah
+ js 0x96e
+ mov ecx, 0xafdca604
+ stosd
+ into
+ adc esi, [ecx+0xae17d828]
+ rcr byte [ebp+0x3a], 1
+ sub [ecx], eax
+ mov ebp, 0xffd342cb
+ and ah, ch
+ push esp
+ loope 0x9b4
+ dec ebp
+ xor dl, bl
+ out dx, al
+ mov [edi], esi
+ jl 0x982
+ invalid
+ fld qword [ebp-0x7c]
+ insd
+ wait
+ dec edi
+ push edi
+ adc ebx, [edx-0x27]
+ salc
+ xor dword [ecx], 0x5c
+ dec byte [esi-0x3f]
+ or [edx], eax
+ xchg edx, eax
+ into
+ outsd
+ xor [edi+0x84314b77], edx
+ lea edx, [ecx+ebp*2-0xd]
+ mov edx, 0xbe94bcdf
+ mov ecx, 0x1314367e
+ push ss
+ lock shl byte [ebx], 0x56
+ mov [esi+0x194b4c6c], ss
+ out 0xbb, al
+ sub ecx, eax
+ or al, 0xaf
+ jno 0xa19
+ das
+ dec esi
+ popfd
+ xor [ecx+0x2d0988f6], esp
+ wait
+ mov eax, [0xbfbf9891]
+ pop esp
+ popad
+ add dl, [eax+0xc17c5d02]
+ xlatb
+ push cs
+ iretd
+ std
+ int3
+ stosd
+ shl dword [edx-0x34], 1
+ cmp dl, dh
+ jno 0xa01
+ adc dl, [edx+0xa271ac71]
+ salc
+ push ecx
+ int3
+ jmp dword 0xbe7e:0xdd399c2e
+ cmp byte [eax], 0x67
+ pop edi
+ jle 0xa98
+ in al, 0x2f
+ adc [ebx], eax
+ idiv ebp
+ push es
+ lea ebp, [edx-0x6e]
+ inc ebp
+ pop esi
+ xor [0x1aee8ce4], esp
+ jz 0xaa5
+ into
+ sahf
+ shl dword [esi+0x47], 0xf0
+ movsd
+ inc ebp
+ rol dword [ecx+0x1b142a6a], 1
+ int3
+ mov cl, 0x8a
+ lock repne cmp eax, ebp
+ mov [esi+ebx*8], al
+ add al, 0x91
+ arpl [edi], dx
+ jnz 0xa6c
+ push cs
+ adc ecx, [edi+0x7a]
+ jp 0xa88
+ aaa
+ push ebx
+ mov [ebp-0x32], bh
+ or al, 0x23
+ iretd
+ inc edx
+ psubusb mm7, mm4
+ jecxz 0xaaf
+ das
+ das
+ xchg ebx, eax
+ mov dl, 0x8e
+ test al, 0xcd
+ invalid
+ adc al, 0x5b
+ sbb eax, 0x708660b
+ repne shl al, 0xf5
+ pop es
+ salc
+ xchg ebx, eax
+ imul eax, [ebx], 0x59d49ea2
+ xchg ecx, eax
+ dec ecx
+ invalid
+ adc al, ah
+ jmp dword 0xe3e8:0xe4234f72
+ test [eax], ebp
+ fnstsw word [ecx-0x5f]
+ xor byte [eax+0xef750efc], 0xb9
+ mov [0x39baf1b0], al
+ xchg esp, eax
+ std
+ popad
+ fbstp [ecx+ebp*4]
+ dec ebx
+ cs movsb
+ in al, dx
+ mov ecx, 0x8ee46992
+ inc esp
+ mov edx, 0xf73d610b
+ test [ebx+ebx], ebx
+ insd
+ mov ch, 0x66
+ sbb eax, [edx+0x9a393107]
+ call 0xfffffffff9747199
+ btc [ecx], edi
+ pop ss
+ jl 0xb20
+ jecxz 0xb2f
+ scasd
+ cmpsb
+ lahf
+ push ds
+ add al, 0x97
+ pushfd
+ salc
+ aad 0x6
+ popad
+ aam 0x72
+ enter 0xfba7, 0x60
+ out dx, eax
+ mov [edx+0x43], eax
+ inc ebx
+ xor eax, 0x604a48
+ fdiv qword [ebp-0x13]
+ cdq
+ and eax, 0xe70452e6
+ lahf
+ push ds
+ jz 0xb01
+ push ebx
+ or esp, [ebx-0x16]
+ fbstp [edi]
+ xor dword [esi+esi+0x5a920d7f], 0xc38b1a72
+ lds eax, [esi-0x2f]
+ inc eax
+ clc
+ push dword 0xb5f787ab
+ cmp [0xbb7e95fa], ebp
+ dec ebp
+ test [edi+0x748ab13c], esp
+ push ds
+ and dl, [esi]
+ xchg [eax+eax*8+0x366852ed], bh
+ pop eax
+ in eax, dx
+ stosb
+ popfd
+ cli
+ inc ebx
+ jmp dword 0xd912:0x1549a128
+ fisub dword [edx]
+ pop edi
+ sahf
+ std
+ jnp 0xafd
+ push dword 0x657c0db7
+ push edi
+ daa
+ int3
+ mov ch, 0xb4
+ adc eax, 0xfc744747
+ mov dh, 0x9b
+ dec esp
+ jns 0xbcd
+ std
+ xor dh, al
+ push edx
+ mov ebp, 0x95134ff4
+ xor ah, [eax+ecx*2]
+ jg 0xbab
+ push ss
+ test [edx+0xea903694], ecx
+ rep lodsb
+ repne mov ecx, 0x793b9c9e
+ stc
+ stosd
+ adc dh, 0x3e
+ sbb al, 0x4
+ mov [0xcbc2f994], al
+ jb 0xb2c
+ pop ds
+ pop ss
+ sar dword [0x44386b47], 0xbe
+ and bl, [ecx+0xf86fc66b]
+ mov ch, 0x93
+ pop edx
+ int 0x82
+ xchg edi, eax
+ mov bl, [ebx-0x56]
+ stosb
+ call dword 0x4f82:0xb4db446
+ or ch, [ebp-0x76]
+ js 0xb49
+ or [eax+esi+0x3f1aae4d], ecx
+ jp 0xb5b
+ movsd
+ outsb
+ nop
+ sub ecx, [edx]
+ inc ebp
+ out dx, al
+ sub eax, [edx]
+ stc
+ pop edi
+ adc al, 0xbf
+ repne mov eax, [0xd45f0f35]
+ jnz 0xc2c
+ out dx, al
+ fsubr dword [ebx+0x1d]
+ mov esp, 0xe0696e72
+ js 0xb9d
+ or [eax], ebp
+ pop es
+ lock and [ebx+0x55], ch
+ test al, 0xca
+ cmpsd
+ xor al, 0xdb
+ dec esi
+ lock mov cl, bl
+ pop ebp
+ call dword 0x7026:0xe705bccd
+ dec esi
+ dec esp
+ mov ch, 0x50
+ xlatb
+ test [eax+0x66e4487a], eax
+ or eax, 0xd31061f4
+ call 0xffffffffb945a135
+ repne call dword 0x500c:0x815bd97e
+ push esp
+ pop edx
+ jecxz 0xbdf
+ fisubr word [edx]
+ popfd
+ out dx, eax
+ and [esi], bh
+ mov ebx, 0x8089623
+ push edx
+ jo 0xc82
+ xor ch, [edx+0x4]
+ jb 0xc04
+ inc ebx
+ cmc
+ neg byte [esi-0x53]
+ pop edx
+ sbb al, 0x3f
+ lds edi, [ecx+0xafa84356]
+ nop
+ mov al, 0xb5
+ or byte [eax+0x71], 0x43
+ xchg edx, eax
+ aam 0x63
+ call dword 0xee37:0xed2ec16a
+ adc eax, 0xa897a4b9
+ a16 jz 0xc46
+ movsb
+ imul esi, [esi+0x53fbc5a1], 0x5a
+ jg 0xbda
+ or byte [edi+0x9f367649], 0x7d
+ push eax
+ imul edi, [eax], 0x2c4aa59b
+ sub [ebp+0x3e], bl
+ and ebx, [ecx+0xce880d08]
+ inc esp
+ sub [ebp+0x11], ecx
+ pop esp
+ dec ecx
+ push ebp
+ salc
+ mov ah, 0x36
+ jge 0xc35
+ jnp 0xcb2
+ pop edx
+ inc ecx
+ inc ebx
+ or ch, al
+ sub [ebx], ch
+ o16 jb 0xcf9
+ das
+ sub eax, 0xc6c32927
+ mov [0xe262d532], eax
+ inc ebp
+ out dx, al
+ xchg ebx, eax
+ int 0x3c
+ arpl [ecx+0xd89bdfe3], di
+ invalid
+ lock invalid
+ xchg al, ch
+ add eax, 0x359ed371
+ sub al, [edi+0x6932c6c5]
+ jmp 0xc39
+ xlatb
+ push cs
+ xor dh, [edi]
+ arpl [esp+edi*2], cx
+ test al, 0x4e
+ fbld [ecx+ecx*2-0xd]
+ pop eax
+ pop edi
+ add dword [edi+0x56ca6c2a], 0x15
+ scasb
+ invalid
+ sbb eax, 0xa744404f
+ int 0x66
+ sbb [esi], esi
+ and [esi], esi
+ invalid
+ sub bh, cl
+ call 0xffffffffc8bd8c41
+ adc bl, [esi]
+ stosd
+ jz 0xcf3
+ rol ah, 1
+ int1
+ mov bl, 0x4b
+ push es
+ or al, 0xd5
+ imul ecx, [edx+0x1c187bd3], 0x6f7bffe8
+ sbb edi, ebp
+ push ebx
+ test al, 0x4a
+ fidivr word [ebx+0xdbd472e7]
+ mov [0xfa1e3ac4], eax
+ xchg edi, eax
+ ret
+ push edx
+ push edi
+ push ss
+ dec esi
+ adc al, ch
+ wait
+ cdq
+ out dx, al
+ test [ebx+0xd8898cac], ecx
+ fcom dword [eax-0x25]
+ stosb
+ lahf
+ a16 mov ebx, 0xeceb1d22
+ rcl byte [ecx+0xcca9c686], 1
+ leave
+ and dh, [edi+0x109fe867]
+ retf
+ mov edi, 0x7c84aa58
+ cld
+ cmp esp, ebx
+ xchg [ebx-0x6a], edx
+ push ds
+ mov cr1, [ebp+0x1b]
+ push ss
+ cli
+ xor ecx, [eax+0xdc5cca8e]
+ jb 0xd25
+ imul ebx, ebx, 0x30976844
+ sbb eax, 0xd37c2cb
+ das
+ inc eax
+ xor dword [esi], 0x1db6cb00
+ mov cl, 0x2c
+ mov [esi-0x6f], edi
+ leave
+ mov [ebx], bh
+ imul eax, [esi], 0x894b630a
+ add eax, [esi+0x65]
+ xchg edi, eax
+ sub edi, edx
+ inc esi
+ repne or ebp, [eax-0x58]
+ loope 0xcfb
+ sub eax, 0x4b9f573e
+ lea edx, [edi]
+ in al, 0x80
+ jae 0xd7d
+ xchg edi, eax
+ sbb al, 0x22
+ sbb byte [edi+0x96c61637], 0x52
+ jno 0xda6
+ pop es
+ dec esp
+ ret 0xc7e4
+ push ss
+ fbld [ebx]
+ mov edi, 0x10ad479b
+ repne sahf
+ sbb ch, [eax+0x39b6e4c7]
+ fmul qword [ecx+0x7b14c8c2]
+ xchg edi, eax
+ int1
+ mov ebx, [ecx+esi]
+ fxch7 st0
+ inc ecx
+ pop edi
+ popfd
+ xor eax, 0x78b5d870
+ mov esp, 0x72aa7c3b
+ cmp eax, 0xdca682af
+ das
+ shl dword [esp+ebp-0xc], cl
+ std
+ xor al, 0x1d
+ inc esi
+ or eax, 0x84135706
+ int1
+ pushad
+ out 0xfe, al
+ test byte [eax-0x6c], 0x2f
+ arpl [esi+0x37], bp
+ or al, 0xa8
+ xor [edx], ah
+ xchg esi, eax
+ xchg ecx, eax
+ add [edx+0x8], al
+ jl 0xdf6
+ ficom dword [esi]
+ and byte [ecx], 0xbe
+ and al, 0xfd
+ test esi, esi
+ sub al, 0x33
+ int1
+ jbe 0xe3c
+ push cs
+ xor al, 0x89
+ mov ebp, 0x24ea9942
+ push ecx
+ jnz 0xddc
+ invalid
+ retf
+ inc edx
+ scasb
+ or byte [ecx-0x5e], 0x10
+ fimul dword [edi+0x76]
+ imul ebp, [ebp+0x8532a334], 0x1365310f
+ add eax, 0x9236756a
+ mov bh, 0x9f
+ mov eax, 0xc973540d
+ xor eax, 0xd144f52
+ rol byte [ebp+0xc595556b], 0x1f
+ jae 0xea7
+ xor [esi+0x58], ebx
+ or bl, [ecx]
+ and ebx, [edx-0x6]
+ test [edi+0x4b2ab0c5], dh
+ and edi, [ecx+0xc6e40c95]
+ stc
+ mov al, [0x4da547be]
+ and edi, [ebp+0x71]
+ xlatb
+ lock jbe 0xec9
+ mov ch, 0xa9
+ cmp [edx+0x52], esp
+ xor al, 0x22
+ pop es
+ sub dh, 0x45
+ sub eax, 0xb234d79d
+ mov bh, 0x55
+ mov ecx, 0x2e32c2c1
+ pop eax
+ or eax, [ebx+0xac8ed1]
+ das
+ sub eax, 0x894f5fde
+ push dword 0xe04e1ab1
+ stosd
+ out 0xbc, eax
+ pop ebp
+ and eax, 0x4f828d00
+ nop
+ push ebx
+ xor al, 0x20
+ jno 0xe8c
+ sbb dword [ebx+0x23ce924], 0xf8a9277e
+ mov dl, 0xb
+ fcomp3 st6
+ inc ebx
+ out dx, al
+ sub [ebx+0x2a1886ca], edx
+ ficomp dword [ecx+0x523e59e8]
+ cmp [ebx+eax*4], ebp
+ in al, 0xdc
+ pop esi
+ not dword [edx+0x49]
+ lodsb
+ in al, 0x43
+ push ds
+ mov [0xfc88276e], eax
+ pop edx
+ call dword 0xa3f2:0xefb5d5e5
+ call dword 0xec8c:0xfa02217a
+ mov [0x86e676c2], eax
+ nop
+ cmp dh, [0x2711a265]
+ add dh, dl
+ cmpsd
+ ficomp dword [ecx+0x6393bcdf]
+ mov cl, 0x51
+ cli
+ popfd
+ push ss
+ push ebp
+ adc [ebp+0x90438571], ah
+ add ebp, ebx
+ maskmovq mm2, [eax-0x17]
+ js 0xee5
+ mov dl, bh
+ push edi
+ push edi
+ shr eax, cl
+ or eax, 0x25e8312c
+ xchg ebx, eax
+ dec edi
+ sbb al, 0x80
+ and esi, [ecx]
+ test al, 0x14
+ pushad
+ ret
+ inc ecx
+ adc [esi+0x3b], esp
+ invalid
+ cmp ebx, [ecx-0x34]
+ rol byte [esi+0x477b9d74], cl
+ sbb eax, ebx
+ cdq
+ push ebx
+ invalid
+ ja 0xf88
+ dec esi
+ invalid
+ adc eax, 0x35fd79c6
+ wait
+ xchg [ebp+0x941af95b], ebp
+ fbld [eax+0xe3469796]
+ stosb
+ mov [edx+0x22], cr0
+ xchg edi, eax
+ imul esi, edi, 0xa2b53f5f
+ push eax
+ cmp [ecx+ebp*4], esp
+ bound ebx, [esi]
+ or esi, edi
+ loope 0xf83
+ outsd
+ call 0xffffffff96f1a13f
+ invalid
+ sti
+ mov ecx, 0x2bb9610f
+ lahf
+ and bh, [ebx+0x4bf49c08]
+ imul dword [ebx-0x19]
+ test al, 0x67
+ shl dword [edx], 0x17
+ in eax, 0xfd
+ wait
+ cmp eax, 0x816f37f
+ adc [eax], ebp
+ push dword 0x844dd8cf
+ sub al, [ecx]
+ stosb
+ shr dword [eax+0x5a994de7], 0xd
+ inc ecx
+ mov edi, 0x35e63e4c
+ cwde
+ add [edi-0xa], ch
+ sub al, 0x99
+ jle 0xf79
+ push esi
+ cmpsb
+ inc ecx
+ sub dword [fs:eax+0x68], 0x7ef16c89
+ xor [esi-0x4e], dh
+ cmp al, 0xa4
+ ror byte [esi+0x4d005502], 0x8
+ scasb
+ mul edi
+ aaa
+ out 0x11, al
+ or ah, [edi+0x7ee5927a]
+ fxch4 st1
+ pop ecx
+ add al, 0x60
+ inc ebp
+ pushad
+ xor bl, [ebx+0x35f387ce]
+ add al, [edi+0x1c8087e3]
+ sahf
+ sub esi, ecx
+ invalid
+ dec edx
+ outsb
+ and al, 0x50
+ popfd
+ pop ebp
+ int 0x92
+ rcl dword [ebp+0x19f7c430], 1
+ iretd
+ mov [0x9814d961], al
+ push ss
+ stosd
+ mov al, [0xe6444d13]
+ sub [ebx+0xfef7182a], edx
+ sub eax, 0x8fd0971c
+ push edx
+ sbb ecx, esp
+ retf 0x3ab0
+ xor al, 0x97
+ adc [eax], edi
+ jle 0xf8d
+ adc [ebx+0x12ac2e1d], edi
+ rcl ebx, 1
+ jnp 0xfa9
+ fist dword [edi+esi*8+0x61]
+ ja 0xfb0
+ scasd
+ push eax
+ mov esp, 0x4e0f5827
+ dec edi
+ stc
+ invalid
+ jnp 0x1027
+ xchg esp, eax
+ push ebx
+ push edi
+ jnz 0x105f
+ mov [0x929b4468], eax
+ sub al, 0x57
+ and dword [esi+esi*4+0xe029656], 0x718b6ad2
+ xchg esi, eax
+ clc
+ aas
+ xchg ecx, eax
+ jmp 0x41fee261
+ invalid
+ cmp byte [esp+ecx], 0xd0
+ pop eax
+ dec ebp
+ jp 0x1051
+ outsd
+ test al, 0x78
+ mov bh, 0xd3
+ out 0x69, eax
+ mov [0x3a661122], al
+ aad 0xf7
+ pop esp
+ xor [ecx-0x4f], esp
+ iretd
+ dec edi
+ mov [eax], ds
+ mov [0x6689ce77], al
+ adc eax, [eax+0x9b08b3b8]
+ sbb [ecx], esi
+ shr esp, cl
+ js 0x1035
+ jmp 0x20210c31
+ aas
+ cmpsd
+ jge 0x1090
+ mov [edi+0x6445aac3], cr1
+ test [eax+0x57], ebp
+ push eax
+ in al, 0x10
+ int3
+ loope 0x1051
+ jns 0x1054
+ call 0xffffffff8df4850a
+ mov ah, 0x7c
+ sar dword [edx+eax], 1
+ mov esi, 0x2ededbe8
+ rol dword [ebx+0x1d65e59b], 0x60
+ scasd
+ mov cl, 0xe0
+ dec edx
+ or [ecx-0x6d], edi
+ daa
+ add al, 0x7c
+ into
+ adc esp, 0x5101715
+ jnz 0x1089
+ sbb al, 0x4d
+ dec edi
+ or ah, [edx]
+ push dword 0x4c073002
+ dec edx
+ o16 cld
+ sbb [fs:esi], bl
+ ja 0x103c
+ pop ebp
+ push ebp
+ retf 0xb295
+ push esi
+ lfs edx, [ebp+0xdd081c59]
+ mov [eax+0xa8511d4], cl
+ invalid
+ iretd
+ call dword 0x8140:0x5a3afeb
+ jecxz 0x1123
+ xchg edi, eax
+ call dword 0xf0aa:0x9856f431
+ stosd
+ push esi
+ or eax, 0x5769a868
+ fnstenv [ebx+eax*2+0x3a]
+ fmul qword [edx-0x76]
+ pop ss
+ pop ebp
+ jle 0x10a3
+ pop ebx
+ adc eax, 0x90e1b11f
+ out dx, eax
+ xchg esp, eax
+ dec ecx
+ cmpsd
+ xchg esi, eax
+ sub edi, ebp
+ imul byte [edi+0x90a85bb]
+ rcl ebx, 1
+ mov esi, 0x2e7eab26
+ loopnz 0x10eb
+ jae 0x1180
+ clc
+ out 0x76, al
+ pop eax
+ loop 0x1137
+ mov [0x44d0fdf], al
+ adc ecx, [esi+0x2e]
+ mov ch, 0xde
+ retf 0x2df
+ in eax, dx
+ loopnz 0x10ad
+ and dl, [ebp+0x28]
+ invalid
+ cmp [eax*4+0xf6612c8b], dl
+ movsd
+ lodsd
+ cmp eax, [edx+0x954bbe12]
+ push eax
+ int1
+ lodsd
+ jo 0x110b
+ pop esi
+ push edx
+ mov al, ah
+ iretd
+ push ebp
+ add eax, 0x3014be2a
+ xchg ecx, eax
+ cmp esi, [ecx+0x8]
+ ret 0x6b83
+ mov dh, 0xbe
+ insb
+ arpl [edx], cx
+ and [edi], edx
+ clc
+ loope 0x10e3
+ rep cdq
+ pop ds
+ jnp 0x110f
+ sbb eax, 0x9a64c8f1
+ mov bh, 0x98
+ sub [edi+0xd9e81ab1], edx
+ into
+ push ecx
+ mov [0xb884f280], eax
+ sti
+ nop
+ xchg edi, eax
+ push edi
+ js 0x117e
+ repne insb
+ rcpps xmm4, xmm7
+ fstp qword [0x67acc747]
+ add edx, [ecx+0x8a9204f2]
+ das
+ lds edx, [ebp+0x18]
+ cmp al, 0xce
+ popfd
+ rcr byte [ebp-0x24], 1
+ jns 0x113f
+ adc esp, [0x449f06e8]
+ mov esp, 0x81827652
+ std
+ leave
+ into
+ invalid
+ push cs
+ mov ecx, 0x83ba4d00
+ cmc
+ sbb eax, 0x4233b376
+ pop ebp
+ push cs
+ pop ss
+ repne rcl dword [eax], 0x25
+ invalid
+ jb 0x11db
+ test al, 0xb6
+ lodsd
+ loope 0x11f6
+ into
+ jecxz 0x11fb
+ xlatb
+ push esp
+ rol dword [edi], 0x91
+ mov cl, [edi+0x7c227c17]
+ mov [0x4ab6de35], eax
+ mov edi, 0x41fc12f1
+ retf
+ or al, 0xe5
+ and al, 0xe3
+ std
+ mov [edi+esi*2+0xe9ac9bb6], cr0
+ mov eax, [0xf6a896cb]
+ and al, 0xfe
+ out dx, eax
+ dec esi
+ pushfd
+ xchg ebp, eax
+ xchg esi, eax
+ xor cl, [ebx]
+ adc dword [edx], 0x1d
+ push 0x1b
+ out dx, eax
+ xor eax, 0xead77ae7
+ ret
+ or [edx], ch
+ o16 salc
+ pop edx
+ jb 0x11da
+ dec ebx
+ or bl, bh
+ lahf
+ call 0x7374fe67
+ or [eax+0x1e], edx
+ in eax, dx
+ jmp 0x1252
+ push dword 0x44fc27c4
+ sahf
+ pushad
+ int 0x97
+ aad 0x64
+ int1
+ add eax, 0x2db9f27a
+ dec eax
+ sbb esp, edi
+ push ds
+ cmp eax, ebp
+ jmp 0x11e8
+ mov al, [0x899bd4d5]
+ sbb eax, 0xb615e1c0
+ sub dh, [ecx+0xe3ae225]
+ and dword [ecx-0x76], 0xb99f8636
+ test [ecx+0xc7bba943], cl
+ xor [edi-0x3d], dl
+ sbb eax, [eax]
+ xchg [edx], bl
+ mov [0xab0c392e], al
+ hlt
+ insb
+ inc ebx
+ or [eax+ebx*2-0x62], bl
+ out dx, al
+ mov [0xe52d324f], eax
+ dec edi
+ pop edx
+ mov al, [0xabf8316e]
+ test [edx], bh
+ shr dword [edi], 1
+ fadd st1, st0
+ inc edi
+ fidivr word [ebp-0x2d]
+ pop esp
+ mov ecx, ss
+ out dx, eax
+ invalid
+ add al, 0xb6
+ jo 0x1276
+ shr word [ecx], 1
+ invalid
+ push ebp
+ retf 0x8a07
+ neg byte [esi+0x2e311678]
+ salc
+ ror dword [edi+0x7d1712ae], 1
+ pop ebp
+ cmp al, 0xd6
+ shr byte [ecx-0x76], 0xab
+ jae 0x1317
+ adc eax, esi
+ mov bl, 0x2a
+ mov al, [0x1efe9cf]
+ jz 0x131f
+ sbb ah, [edi-0x72]
+ cmpsb
+ mov eax, 0x3dd9209
+ test [ecx+0x4], ch
+ shl [ebx+0xe7b11174], cl
+ shl byte [eax+ebx*2-0x23], 1
+ test eax, 0xad5699b6
+ insb
+ rep int 0xc5
+ imul esi, [esi+0xd418baf4], 0xdc3e6aa9
+ mov al, [0x14f5a367]
+ fcmove st0, st1
+ sbb [edx-0x64], esp
+ cmp eax, 0x3f7b46d1
+ pop ss
+ xchg ebx, eax
+ std
+ out dx, al
+ in al, 0x2d
+ sub [ecx+ebp*4+0x3257ed1b], ecx
+ hlt
+ retf 0x52a7
+ repne daa
+ clc
+ jp 0x1372
+ pop ecx
+ mov ch, 0x16
+ pop edi
+ movsd
+ inc esp
+ mov al, [0xf676f88]
+ movsd
+ lea ebx, [edi]
+ salc
+ pop ds
+ add cl, bh
+ push ss
+ dec eax
+ ret
+ lds edi, [edi+0x9aa0bc93]
+ fst qword [ebp-0x60]
+ xor ch, [ecx-0xc]
+ o16 jl 0x131b
+ int1
+ dec edx
+ jg 0x134d
+ pop ebx
+ pop ss
+ cmp al, 0x16
+ and ecx, ecx
+ push esp
+ into
+ sti
+ mov eax, [0x2e5f2e6d]
+ cmp bl, [ebx]
+ fprem1
+ inc ebp
+ a16 outsd
+ pushad
+ inc ecx
+ fidivr word [edi+0x19a7fbfd]
+ les eax, [edi]
+ in eax, 0x3a
+ push ds
+ imul esp, [ebp+0xb22daf9a], 0xf9b49a78
+ sbb byte [gs:ebp+0x9452f2a0], 0xeb
+ mov dh, 0x5a
+ loopnz 0x1307
+ or [0xc91f31f1], ch
+ sbb eax, ebp
+ outsb
+ push ss
+ invalid
+ mov ebx, 0xd15a3fdb
+ and ebp, ebx
+ movsb
+ cmpsd
+ jmp dword 0x69f8:0xf3d094f7
+ add al, 0x4e
+ xchg [esi], esp
+ sbb [ecx+0x6f], esi
+ pop eax
+ push ds
+ mov fs, [eax+0xcfd6d55c]
+ arpl [edx+0x4d], sp
+ mov dl, dh
+ scasd
+ xlatb
+ sub bl, [eax+0xcdd52985]
+ mov eax, [0x9a135194]
+ xor eax, 0xce07ef5f
+ push eax
+ mov ss, ebp
+ insb
+ and byte [ebp+eax*4-0x54], 0x9f
+ push esp
+ mov esp, 0xe5950f68
+ mov al, [0x9dfefe12]
+ lodsd
+ repne jno 0x139c
+ jb 0x13ca
+ xlatb
+ or [ebx], esp
+ popad
+ jp 0x1370
+ call dword far [edx+ecx*8+0x9a417f96]
+ mov esi, 0xe6ba140e
+ loope 0x135f
+ int1
+ add dl, bl
+ shl dword [edx], cl
+ cmp ah, bh
+ adc eax, 0x6ce8b335
+ shr cl, 1
+ fst dword [ss:ebp+0x1548eb37]
+ adc al, 0x16
+ mov dword [esi], 0x9b74e96e
+ mov al, [0xd7d81053]
+ mov ebp, 0xa9ecffe0
+ and ecx, ecx
+ jb 0x13f1
+ invalid
+ cdq
+ scasd
+ push 0xa3
+ movsd
+ jno 0x13fa
+ int1
+ popfd
+ inc ebp
+ ret 0x7d8
+ inc edx
+ mov ax, 0x3b54
+ imul esp, [ecx], 0x49ee5bc3
+ pop esp
+ and eax, 0x910ef28a
+ dec esp
+ xchg esi, eax
+ stc
+ jle 0x143a
+ jmp 0x13c2
+ test [0xcd2f4cd4], ebp
+ mov esi, 0xa806610a
+ fnstcw word [eax+0xe1224195]
+ xchg edx, eax
+ cmpsd
+ inc esp
+ push esi
+ sbb [eax+edi*4], ebp
+ leave
+ fld dword [edx+0xa557439d]
+ mov ecx, [edi+0x582c6389]
+ test eax, 0x22d7aebd
+ js 0x1429
+ sar dword [edx+0x4f332cec], 0xdf
+ xor cl, ah
+ mov [0x9c31a845], al
+ dec esp
+ inc edx
+ add [ebx+esi+0xffba64f4], esp
+ std
+ jbe 0x13fc
+ cmp edi, [ecx+0x55843717]
+ xchg ebx, eax
+ enter 0xd9ab, 0xfc
+ rcl byte [ebp+0x3f], cl
+ adc [edx+0x834fddb3], eax
+ sub al, 0x3a
+ mov al, [0xc6bb70d2]
+ and [edx-0x32], eax
+ jnz 0x14d0
+ pop esp
+ or [ecx-0x61], ch
+ sub bh, 0xe4
+ out 0xe3, al
+ mov ah, ah
+ cmp cl, bl
+ xchg ebp, eax
+ js 0x14e2
+ add eax, 0x647dbe38
+ sahf
+ xchg ebx, eax
+ loope 0x14dd
+ popfd
+ mov al, [0x7f296e05]
+ cmp eax, 0x283b3c3b
+ sub al, 0xb8
+ inc esp
+ wait
+ xchg ebx, eax
+ and [ecx], esi
+ mov ecx, 0x26b9bfa3
+ mov ah, 0xe
+ les eax, [edx-0x1f]
+ jle 0x151b
+ movsb
+ lock sbb al, 0x1a
+ jl 0x14ad
+ sub al, 0x21
+ test [ebx], dl
+ add eax, esi
+ insd
+ inc ebp
+ cmc
+ xor eax, 0x58f5af66
+ enter 0xa7, 0xa9
+ or dword [edx], 0xba
+ inc esi
+ mov ebx, 0xe87ff0ca
+ jmp dword 0xd22f:0x3c694d5e
+ inc edi
+ int1
+ in eax, 0x77
+ out dx, al
+ and al, 0xf7
+ stosd
+ and [eax+0xa00fbaac], ah
+ push esi
+ jnz 0x14bc
+ jz 0x1540
+ into
+ inc esi
+ mov al, [0xf9978476]
+ inc edi
+ ret 0x77ca
+ adc eax, 0xf17e329d
+ mov ch, 0xad
+ repne dec esi
+ fisub word [ecx]
+ mov bh, 0x95
+ scasd
+ mov ebp, 0xe42974fa
+ shl dword [cs:eax+0x7d], 0xb5
+ bound edx, [edx]
+ outsd
+ fsubr st0, st5
+ fcom qword [ecx-0x57]
+ cwde
+ bound edx, [edx+0x7f]
+ push eax
+ dec edi
+ cdq
+ pop es
+ inc byte [esp]
+ or ah, ch
+ pop ds
+ lea esp, [edx]
+ mov esi, 0x22fa717f
+ lock mov dh, 0x1d
+ jb 0x14ca
+ sub eax, 0xe4721f1d
+ out dx, al
+ wait
+ adc al, [ecx+0x7e159d2e]
+ xchg [eax+0x59], cl
+ dec ebp
+ retf 0xd5f8
+ lock mov ah, al
+ lahf
+ mov [0x394bf5ea], al
+ test al, 0x45
+ out 0x11, al
+ fidivr dword [ebx]
+ cmp esp, esp
+ xor al, 0x1
+ lahf
+ pop eax
+ sbb ebp, [ecx]
+ pop esp
+ jmp 0x15a1
+ adc [eax+0xae82cca9], edi
+ mov ebx, 0x4081775a
+ push ecx
+ and dh, [edi+0x167a0a1c]
+ aad 0x60
+ or al, 0x84
+ cmp eax, 0x9ca782ad
+ xchg [edx+0x2], ecx
+ add [ecx+0xda06ed7], ch
+ or [ecx+0x155f52cb], dl
+ daa
+ sub eax, 0x5c5c79e3
+ push ebx
+ arpl [edi+ecx*4], bp
+ jns 0x1558
+ dec ecx
+ mov eax, 0xa9a984a2
+ test al, 0xd2
+ adc edx, ebp
+ mov bh, [esi]
+ xor dl, al
+ xchg [edx], dh
+ o16 mov ah, 0xc3
+ wait
+ add [ebx-0x4], cl
+ inc ebx
+ repne iretd
+ xor dh, [eax]
+ outsb
+ mov [ebx], gs
+ leave
+ add edx, ebx
+ inc ecx
+ push edx
+ ret
+ sub al, 0x73
+ jz 0x15c4
+ jz 0x15e1
+ imul dword [ecx+0xc6423607]
+ movsd
+ pop edi
+ std
+ adc eax, 0xa9a370cb
+ fdivr qword [edi]
+ and ah, 0xe2
+ stosd
+ dec edi
+ aam 0x42
+ jg 0x15dc
+ movsb
+ test edi, esp
+ inc esp
+ adc bh, bl
+ a16 jmp 0x3f9e287b
+ int3
+ jp 0x1619
+ in eax, 0xad
+ rcr dword [edi+0x7cc0d60a], 1
+ invalid
+ cmc
+ adc edx, ebp
+ mov al, dl
+ sub bh, [ebp+0x9386cb04]
+ sbb [ecx+0x6], edi
+ adc al, 0xe4
+ pop es
+ mov bl, 0x1e
+ rcr dword [eax-0x5b], 0x13
+ push es
+ and eax, 0xf37ffe65
+ push edi
+ xchg edx, eax
+ and eax, 0x23999b38
+ rcl byte [0x1181eca], 0x2f
+ cmpsb
+ call dword 0xbe08:0xae7022fd
+ salc
+ ja 0x16ac
+ fidiv dword [ebx]
+ jnz 0x1613
+ jno 0x1612
+ hlt
+ clc
+ push ss
+ adc ah, 0xaf
+ popad
+ dec edi
+ mov [0x6ed1dcaf], al
+ mov al, [0x56eabb59]
+ inc eax
+ cmp ebx, ebp
+ fnstenv [edx+0x91718544]
+ sbb eax, 0xc47a9a29
+ lea ebp, [edx]
+ popfd
+ jno 0x1626
+ in al, 0x9e
+ push esi
+ a16 hlt
+ daa
+ mov [0x905effe7], al
+ xchg ebx, eax
+ enter 0x1efc, 0xff
+ aam 0xba
+ loopnz 0x161f
+ jmp 0x4868ed2b
+ test esp, ebp
+ a16 pop ebp
+ cmp ah, [edi+0x30]
+ out 0xe6, al
+ sub eax, [esi]
+ salc
+ jge 0x16b3
+ dec ecx
+ clc
+ adc byte [ds:edx-0x1e], 0x3e
+ rep fstp qword [edi]
+ push ecx
+ xchg esi, eax
+ test al, 0x96
+ stc
+ jz 0x1661
+ mov esi, 0x49cfb604
+ or eax, 0x6ea9445e
+ push 0x77
+ loop 0x1662
+ aas
+ xchg edi, eax
+ invalid
+ invalid
+ lock das
+ cmp eax, 0xce5632a8
+ xor [edx], dl
+ xchg ebp, eax
+ xor al, 0x70
+ mul byte [ebx]
+ shl dword [ebp+0x13], 0x62
+ scasb
+ lds esi, [edi-0x48]
+ outsd
+ xchg edx, eax
+ push ebx
+ out 0xd9, al
+ o16 xor bl, [ebx]
+ int1
+ imul ebp, [esi+0x6418118], 0xbb5f1483
+ sub edx, [0x3ec270c7]
+ xor al, 0xc
+ iretd
+ lahf
+ popad
+ retf 0x474
+ jo 0x168a
+ cmp dl, [ebp+0x439b5eb5]
+ int1
+ invalid
+ mov dh, 0x82
+ mov dh, [ecx+0xbd381018]
+ nop
+ and al, 0xda
+ ja 0x1710
+ mov al, [0x74e37a2]
+ dec esp
+ enter 0x8c8d, 0x2d
+ xchg [ebp+0x4ef79e2c], ebp
+ pop esi
+ xlatb
+ xchg edx, eax
+ lahf
+ cmpsd
+ xor edi, [edi+ebx*4+0x35]
+ mov ah, 0xef
+ xchg [edi-0x74], ah
+ pop esp
+ fisub dword [eax+0x5f7e69a0]
+ adc [ebp+0x56], ch
+ jno 0x177c
+ mov esp, 0xe148d095
+ ret 0x5abf
+ or byte [eax+0x8344b9e2], 0xa1
+ mov edx, 0x793024a1
+ out dx, al
+ add eax, 0x38760464
+ ret 0xf750
+ mov eax, [ebp+0x22334ef8]
+ aaa
+ sbb edx, [edx+0x62a36164]
+ pop esi
+ retf 0x78ab
+ push esi
+ stosb
+ or [edi], ebp
+ or ch, [esi+esi*8+0x67]
+ std
+ jae 0x172e
+ test dword [edi-0x76], 0x4d148686
+ sti
+ pop edx
+ fs lodsb
+ cmc
+ add [0x9ad6f4f], ecx
+ hlt
+ adc ecx, eax
+ mov bl, ch
+ jmp dword 0xe227:0x3bf35c6b
+ fdiv st0, st1
+ or eax, 0x723b6a7b
+ pop ebp
+ inc ecx
+ call 0x61e56998
+ int3
+ sbb edx, [esi]
+ popfd
+ movsb
+ fcom dword [edx]
+ rcr dword [ebp+0xe45455ab], cl
+ test ebp, 0x9be65a09
+ adc [edx], eax
+ out dx, al
+ ficom word [ebp+0x36]
+ imul ebp
+ popad
+ mov esi, 0x422b9112
+ or edx, eax
+ xchg [esi+0x5571090b], bl
+ push es
+ outsb
+ jg 0x17f2
+ cmpsd
+ mov esp, 0x3fb40b93
+ cmpsd
+ xchg esp, eax
+ movsb
+ mov esp, 0xdac30464
+ rep inc ebx
+ pushfd
+ or al, 0x20
+ mov esi, 0x2a8c97b2
+ imul edx, esp, 0xbb0ca76e
+ js 0x17b6
+ jz 0x17eb
+ dec esp
+ jmp dword far [ecx-0xa]
+ mov eax, [0xa1397eef]
+ jbe 0x186b
+ lahf
+ popfd
+ mov [0x5b35f5c8], eax
+ test al, 0xe9
+ xchg ebp, eax
+ mov al, [0xbd7b3ea9]
+ enter 0x77a3, 0x1f
+ test [ebp+0x85ab2579], cl
+ or eax, [ebx]
+ lodsd
+ sub [ecx+0x909980eb], edx
+ imul esp, [0x935cfa8c], 0xc4
+ ret
+ insb
+ xor ch, [edi]
+ retf 0xd0d4
+ nop
+ mov esi, 0x856de28d
+ sahf
+ arpl [esi+0xa10ff2ab], sp
+ pop ss
+ mov cl, 0x0
+ adc al, 0x6c
+ retf
+ aas
+ push cs
+ inc eax
+ inc ebx
+ push 0xe6
+ dec ebp
+ jb 0x183d
+ jmp 0x180e
+ sar al, 0xef
+ loopnz 0x17e6
+ or eax, ebp
+ int3
+ dec byte [ebx-0x2d]
+ stosb
+ wait
+ sub [edi+0xf0ae0922], dl
+ xor eax, 0x4a765e6
+ insd
+ pop eax
+ xchg ebp, eax
+ pushfd
+ pop ebp
+ and eax, 0xdc381f2
+ shl esp, 0x76
+ push eax
+ inc edx
+ or [0xa8d94f4e], cl
+ scasb
+ cmp al, 0x68
+ pop esp
+ scasd
+ add [0x737676eb], dh
+ adc [ebp+0xf4a7402], bl
+ mov al, 0xde
+ out 0x4d, eax
+ mov ebx, [edx+0xa5c12fe]
+ jae 0x18f9
+ sahf
+ xlatb
+ scasb
+ hlt
+ mov ecx, 0x457d4b74
+ out dx, al
+ jns 0x18eb
+ cmc
+ arpl [edi], di
+ sbb eax, 0x20250ec9
+ xchg ecx, eax
+ mov edi, 0x43b176c7
+ iretd
+ pushad
+ aad 0xe6
+ pushfd
+ std
+ pop esp
+ xor al, 0x91
+ push ebx
+ shr [eax], cl
+ mov [0xf35bbb75], eax
+ jnz 0x18a7
+ or al, [edi+0x33]
+ out 0x27, eax
+ rol eax, cl
+ test [ebx+0x3f], dl
+ push edi
+ and eax, 0x32b2babb
+ push esi
+ out 0x5e, eax
+ jo 0x1932
+ outsd
+ stc
+ push esi
+ loop 0x18e2
+ sub [edx+0xedd73d02], eax
+ and [eax+0x4f821eb9], edi
+ xchg edx, eax
+ das
+ jp 0x18f2
+ bound esi, [ebp+0x28]
+ rol byte [edx+0x9453e536], 0x4f
+ jae 0x18e3
+ xchg ebx, eax
+ pop edi
+ out 0x95, eax
+ aam 0x90
+ ret 0x476e
+ iretd
+ sar dword [edx+0x87489f23], cl
+ add byte [eax+edi*4+0x5fc8a2c2], 0x5f
+ out dx, al
+ jno 0x18b4
+ and al, 0xa1
+ xchg edx, eax
+ aad 0x93
+ wait
+ jz 0x197a
+ fild dword [ecx+0xc009371]
+ sub ecx, [eax+0x7979f270]
+ mov edi, ecx
+ invalid
+ mov [eax+0x5cc0975], cs
+ sti
+ mov ecx, 0x1dcf877a
+ fild word [ebp-0x6d]
+ dec ebp
+ in al, 0xb7
+ clc
+ push eax
+ xor ecx, [0x410073a]
+ rcl dword [edx+0xacceaba6], cl
+ pop esi
+ jnp 0x19a4
+ push dword 0x80472ab8
+ adc [ecx+0xc143b03e], dh
+ pop eax
+ push esp
+ push dword 0x6d340323
+ out dx, al
+ mov esp, 0x1c36e32
+ xor ebp, [edi+0xe]
+ mov esi, 0x4c42f9c7
+ xor eax, 0xd6340960
+ push cs
+ pop esp
+ add [ebx+ecx*8], ecx
+ cmp eax, 0x32b1191a
+ dec esi
+ sbb dl, [eax+0x4537a12c]
+ cwde
+ mov ecx, 0xc38677a
+ cmp [eax+0x61fcb9a5], dh
+ sbb [esi+0xa3237468], ebx
+ cmp eax, [edx+0x4e]
+ jz 0x19f0
+ loop 0x195c
+ cmp bh, [0x480f5d21]
+ add cl, [ecx+ebp*4-0x1d]
+ pop ss
+ mov cl, cl
+ mov [esp+ebx+0xd679ae35], ecx
+ in eax, dx
+ xor [ebx+0x2f], ch
+ invalid
+ push edx
+ test [esi+0xa24e80d2], bh
+ outsd
+ stosb
+ add [fs:eax], dl
+ stosb
+ jno 0x19a1
+ arpl [esi+0x57], cx
+ aas
+ mov al, 0xd4
+ sub edi, eax
+ retf 0x3e58
+ cmp [esi-0x1e], edx
+ sti
+ outsb
+ xchg esp, eax
+ loope 0x1a4d
+ jp 0x1a3b
+ les ebx, [edi+ecx]
+ daa
+ invalid
+ retf 0xbf6c
+ mov dh, al
+ mov ebx, [ebp+0x30fd636f]
+ pop ebp
+ xor bh, cl
+ mov [edx-0x6d], ch
+ xchg ecx, eax
+ sti
+ sar dword [ecx+0x40], cl
+ mov ebx, 0x1a7e9f97
+ a16 sti
+ add [esi], al
+ pop ebp
+ fcmovb st0, st2
+ shl dword [edx-0x34], 1
+ push edx
+ push edi
+ push esi
+ push esi
+ jmp dword near [edx+esi+0x78110a68]
+ sbb ebx, eax
+ ror byte [edi-0x38], 1
+ shl dword [ebx], cl
+ call dword far [ecx+edx*2+0xbe0c08f7]
+ cmp byte [ebx*4+0x9279f9c8], 0x49
+ dec esi
+ jo 0x1a4f
+ lodsb
+ or al, 0xca
+ jmp dword 0x8462:0x9c7d7faa
+ dec esi
+ inc ebx
+ inc ecx
+ neg dword [ebx+ebp*8+0x4]
+ stosd
+ mov esp, 0x40475c82
+ insd
+ or [eax+edx*8+0xd49a265c], al
+ bound eax, [edi]
+ xchg ecx, eax
+ pop esi
+ nop
+ pop esp
+ cmp [esi+0xc7ea6095], ah
+ fcmovb st0, st1
+ xchg ecx, eax
+ pop ecx
+ pushfd
+ o16 cmc
+ call 0xffffffff8ce66f4d
+ inc esi
+ dec ecx
+ mov bl, 0xc9
+ daa
+ jo 0x1ac9
+ dec ebx
+ fcomi st0, st5
+ repne outsb
+ invalid
+ or bh, [eax+0x39]
+ sub ah, [eax]
+ mov dl, 0xb3
+ sub al, 0x98
+ push edx
+ mov [eax+0xe], ah
+ shl [edi+0x6eb5866c], cl
+ inc ebp
+ js 0x1aab
+ movsb
+ xchg esp, eax
+ cmp al, 0x46
+ mov eax, [0x8568d8a4]
+ add eax, 0x4fb8fbde
+ insd
+ mov al, 0xa
+ jo 0x1b05
+ xor ebx, esp
+ pop ds
+ js 0x1a86
+ nop
+ pushfd
+ jnz 0x1ae9
+ push esi
+ retf 0x694b
+ rcl byte [edx-0x56], cl
+ out dx, al
+ scasd
+ lds edi, [edi+0xe]
+ sahf
+ imul edx, [eax+0x6ddee1d1], 0xbec11bee
+ sbb [edi+0x39], bh
+ inc ebx
+ mov al, [0x984c8f12]
+ dec esi
+ wait
+ sub [eax-0x48], eax
+ test al, 0x3a
+ add [ebx+0x98d27779], esi
+ jmp 0xfffffffff3e40cd7
+ mov edx, 0x31d63c22
+ dec edx
+ call dword 0xbb46:0x74171464
+ popfd
+ cwde
+ jns 0x1aa5
+ fmul dword [edi]
+ mov [ebx-0x35], edx
+ jle 0x1ac1
+ lodsd
+ pop ss
+ iretd
+ mov [edx+0x781582cd], ch
+ or edi, [edx]
+ add dword [ds:edx+ecx+0xb24566e1], 0x4e
+ add dl, [eax+0xcffce565]
+ invalid
+ dec edi
+ jae 0x1ad4
+ aam 0x6b
+ sbb esi, [edx+0xbb865de6]
+ adc [eax+eax*4], dl
+ fdivrp st1, st0
+ cmp al, 0x91
+ mov edx, [ecx+0x46]
+ sbb al, 0x68
+ outsb
+ adc al, 0x91
+ mov al, 0x9
+ jmp 0xfffffffff0b2372c
+ call dword near [edx]
+ add eax, 0x1b448cbb
+ pop ds
+ mov ch, 0x79
+ out 0xca, eax
+ mov edx, 0x8ab07a67
+ aad 0x51
+ shr edi, 0xb7
+ xor [ebx], edx
+ pop esp
+ mov cr1, eax
+ shl dword [ecx+0x864fe304], cl
+ and [0x5e540579], ebx
+ out 0xe2, eax
+ xor dh, [esi+0x7a]
+ add al, 0xa3
+ call dword 0x469a:0xfd50e644
+ xchg [cs:ecx+0xe023bffd], bh
+ add [ebp+0x13c88cdb], ch
+ dec esi
+ fnstenv [ecx+0x96b54189]
+ sbb ah, cl
+ xchg edi, eax
+ adc cl, ch
+ in al, 0x61
+ jecxz 0x1b3f
+ movsd
+ mov edi, 0xfba7b96
+ xchg ebp, eax
+ dec esp
+ and eax, 0xf98baabd
+ fidivr word [ebx-0x65]
+ adc [ebx+0xaf62d52a], cl
+ invalid
+ js 0x1b68
+ test al, 0x15
+ dec eax
+ sti
+ dec ebx
+ stosb
+ or dh, ch
+ fldenv [0x85448ab9]
+ inc edx
+ in al, dx
+ add bh, [ebx+0x665b4789]
+ mov [edi], dh
+ mov esi, 0xa21f773b
+ inc edx
+ sbb eax, [ebx-0xb]
+ aaa
+ into
+ push esi
+ cmp eax, 0x68b484b6
+ pop esi
+ cmp al, 0x52
+ sbb bl, [ebx+0x3a]
+ mov esp, 0xaed65363
+ mov eax, 0x5e63d139
+ mov dh, 0xe9
+ outsb
+ repne sbb [eax], cx
+ scasd
+ bound eax, [ecx+0x57471095]
+ test cl, al
+ cmp ebp, eax
+ dec eax
+ hlt
+ repne xchg [esi+eax*2-0x54], bl
+ or eax, 0xd8650c5e
+ jnz 0x1bd7
+ cmp bl, bh
+ or [ecx-0x28], ecx
+ ret 0xd22c
+ invalid
+ pop edi
+ scasb
+ xchg [ebp+0x7], ecx
+ pop ds
+ dec eax
+ movsb
+ ret
+ jl 0x1bde
+ pop edx
+ std
+ mov ebp, 0xab4c7bf4
+ dec edi
+ pushad
+ xor al, 0x7a
+ ret 0xf29c
+ invalid
+ sub [esi+0x6687ba93], esp
+ push esp
+ mov dl, 0xbb
+ fldenv [esi]
+ sbb al, 0xa1
+ fstp tword [ebp+0xf597d88d]
+ cmpsd
+ mov al, 0x3f
+ in al, dx
+ cli
+ xchg esp, eax
+ mov edi, 0xb30543cb
+ pop ebx
+ rcr dword [ebx+0x30], 0x67
+ sub dh, [ebp+0x1d]
+ pop edi
+ test [ebx+0x6e], ch
+ inc esp
+ xchg [ebx+0x657aa8b5], esp
+ salc
+ and byte [ecx+0x703156eb], 0xb5
+ sbb ch, [0x16860c65]
+ cmp [eax-0x1d], edx
+ mov es, [edx+0x25cbccdb]
+ xor [ss:eax+0x2c97cfd0], esp
+ cmc
+ dec ecx
+ loop 0x1c87
+ loopnz 0x1c57
+ jnp 0x1c40
+ invalid
+ neg dword [ebx+0x156d414b]
+ nop
+ salc
+ loopnz 0x1bfc
+ movsb
+ das
+ pop ebp
+ out 0x5c, eax
+ push cs
+ invalid
+ push edi
+ adc edi, edx
+ sbb eax, [ebp+0x8d333704]
+ mov es, edx
+ int 0x30
+ outsd
+ mov eax, [0x6de489de]
+ loope 0x1cc0
+ push cs
+ jnz 0x1c64
+ pop ds
+ jge 0x1c94
+ add eax, 0x3dba2e6
+ cmp dh, ch
+ dec eax
+ mov edi, 0x63c90f79
+ insd
+ pop ebp
+ jo 0x1d23
+ nop [edi+0x65]
+ jz 0x1cdc
+ adc cl, ah
+ aaa
+ pop ds
+ mov [0xd7b4ab26], al
+ xchg ebx, eax
+ iretd
+ salc
+ sbb [edi], edi
+ inc edi
+ in al, 0x2c
+ pop ecx
+ pop ebx
+ rep insd
+ scasd
+ add byte [esi], 0xbd
+ pop es
+ mov bh, 0xc9
+ invalid
+ cdq
+ xlatb
+ out dx, eax
+ retf
+ and al, 0x70
+ push ebp
+ push cs
+ pop edi
+ cmp eax, 0x67917e82
+ or esp, ebx
+ retf
+ in al, 0x3a
+ jno 0x1d19
+ cmp [ecx-0x47], bh
+ in al, 0x35
+ mov eax, 0x5264b9bd
+ push esp
+ jo 0x1d1e
+ dec eax
+ mov ah, 0x89
+ rol dword [eax-0x65], cl
+ in eax, 0x2d
+ mov ah, 0x36
+ invalid
+ sti
+ push edx
+ invalid
+ lodsb
+ or al, 0x9d
+ mov eax, 0x170bfc4d
+ sbb dl, [edi+0xb3f1a637]
+ xor al, 0x89
+ int 0x35
+ sahf
+ out 0x81, eax
+ invalid
+ sti
+ xchg ecx, eax
+ retf
+ invalid
+ jmp 0xffffffffdbe510b0
+ push ecx
+ dec ebx
+ jno 0x1cd3
+ fldcw word [esi+0x12d2c7bf]
+ bswap eax
+ mov edi, 0xd7354899
+ aam 0xbf
+ cwde
+ pop ds
+ mov al, 0x5b
+ pop ds
+ ror byte [esi], 0xed
+ or ebx, esi
+ fdivr dword [edi+0x25]
+ xchg [ecx+eax*8-0x47], al
+ sub [0xfcde707f], ecx
+ jae 0x1d67
+ jae 0x1d5c
+ wait
+ cmpsd
+ daa
+ mov edx, 0x8dbce596
+ jle 0x1d8a
+ iretd
+ std
+ lodsb
+ sbb [edx+0x206cc62b], ebp
+ lds ebp, [esi]
+ pushfd
+ jmp 0x1d3e
+ push es
+ pop es
+ mov edi, 0x82cd3871
+ mov edx, 0xb24f9fa6
+ sbb dword [edi+0x3d7a8375], 0x7f3dbb4b
+ lea esi, [ebx+0xb]
+ sub al, 0x7b
+ o16 ja 0x1dc3
+ sar edi, 0xf
+ cdq
+ cwde
+ mov eax, [0x776c0b6c]
+ mov dh, 0xa7
+ add cl, [ecx+0x7e]
+ push esp
+ mov ch, [eax]
+ and edx, esi
+ scasb
+ fcom2 st7
+ fstp qword [eax+edx*8]
+ lodsb
+ push esp
+ jnz 0x1d35
+ out dx, al
+ wait
+ adc ch, [ebx+0x56d5937d]
+ test eax, 0x54713fe4
+ loopnz 0x1d6b
+ xor eax, [ebp+0x72fd7a5e]
+ jmp 0x1dc4
+ in al, 0xfd
+ into
+ a16 mov eax, 0x3c9c07ca
+ invalid
+ dec ecx
+ ret
+ and bl, al
+ mov ebx, gs
+ xor [edi], esi
+ push ss
+ push ecx
+ cdq
+ mov dl, 0x83
+ int1
+ ret 0xb54
+ out dx, al
+ cmp al, 0x92
+ xchg esi, eax
+ sbb dh, cl
+ mov ebx, [edx-0x49]
+ pop es
+ xlatb
+ lodsb
+ imul ebp, [eax+0xa594032b], 0x18
+ nop
+ int1
+ loopnz 0x1df9
+ dec edi
+ mov cl, 0x1a
+ mov ch, al
+ jae 0x1df6
+ inc esp
+ push edi
+ sub al, 0xe4
+ or ah, bl
+ xchg ebx, eax
+ pop ds
+ fsub qword [edx-0x46]
+ out 0xd4, al
+ xor al, ah
+ int3
+ jp 0x1e4e
+ and ecx, esi
+ call 0x31131af9
+ pop edx
+ outsd
+ pop es
+ or [eax+0x4b45f86], edx
+ cmp [ebx-0x13], al
+ ja 0x1e05
+ pop esp
+ jbe 0x1e31
+ jge 0x1e1a
+ enter 0x1445, 0xe4
+ les edi, [esi+0x5e]
+ nop
+ jle 0x1e76
+ aaa
+ ja 0x1ea5
+ ja 0x1e29
+ or [ebx], ecx
+ pop ss
+ movsd
+ xor dl, al
+ add byte [edi], 0x83
+ repne jmp 0x1dc9
+ jmp 0xffffffffe25d2049
+ mov edx, [edx+0x25]
+ mov dl, 0xfe
+ pop esi
+ int1
+ test ebp, edi
+ jmp 0x1e47
+ movsd
+ mov edi, 0x3acb210b
+ jo 0x1e45
+ mov ah, 0x1d
+ and [eax+edx+0x37], bh
+ out dx, al
+ invalid
--- /dev/null
+ mov edi, 0x95804fae
+ int1
+ cli
+ lea eax, [r8]
+ or al, 0xeb
+ invalid
+ add eax, 0xcfca3a9d
+ xor eax, 0xfca13235
+ add dword [gs:rax], 0xf8
+ out dx, eax
+ invalid
+ adc [rsi+0x63], ebp
+ js 0xffffffffffffffe4
+ invalid
+ outsb
+ mov cr1, [rcx-0x6e]
+ jnp 0xffffffffffffffac
+ xchg esi, eax
+ invalid
+ lahf
+ add bl, ch
+ out 0x9f, al
+ sar dword [rcx-0x61], 1
+ invalid
+ invalid
+ invalid
+ jrcxz 0xffffffffffffffbd
+ invalid
+ lock jl 0x81
+ mov ecx, 0xc0d32522
+ out 0x70, eax
+ push rsi
+ invalid
+ invalid
+ in al, dx
+ xchg ecx, eax
+ and ebp, esi
+ push rcx
+ mov cl, 0xc8
+ sbb al, 0x78
+ invalid
+ shr ebp, 1
+ adc bh, [rcx+0x7b]
+ pop qword [rax-0x1]
+ jb 0x3e
+ xlatb
+ invalid
+ add dword [rcx+rdx*8+0x6df499f7], 0x97
+ mov gs, [rsi]
+ loope 0x71
+ mov al, 0x96
+ adc [rbx-0x6d93a7a2], ah
+ ret 0x7e85
+ add ch, ch
+ invalid
+ invalid
+ xchg esi, eax
+ mov bl, 0xe4
+ mov cr0, [rcx-0x250e7f9]
+ inc byte [rbx+rbp*4]
+ sbb dword [rsi+rcx*2], 0x9c886f44
+ push rdi
+ mov ecx, 0xd409a448
+ adc al, 0xe9
+ insd
+ sub cl, bl
+ invalid
+ cmc
+ invalid
+ add [rdi], bl
+ pop rcx
+ mov [rdi], ch
+ xchg edx, eax
+ invalid
+ and [rcx], esp
+ push rbx
+ jbe 0xde
+ mov [rcx], edi
+ sar cl, cl
+ add [rbx+0x5e], cl
+ iretd
+ invalid
+ mov gs, [rdx]
+ adc eax, 0x1107e2e1
+ push rax
+ repne gs movsb
+ scasb
+ a32 jae 0x130
+ ret
+ cmp eax, 0x5fe11475
+ stosd
+ insd
+ xor [rsp+0x69f80098], esi
+ xor eax, ebp
+ int3
+ push 0xc8
+ cmp esi, [rdi-0x643cd6a8]
+ invalid
+ xor al, [rax-0x5eae3741]
+ mov [0x93de01ed705fa0e8], eax
+ xor byte [rcx+0x4f], 0x37
+ ja 0xa6
+ xlatb
+ o16 shl [rax], cl
+ mov bh, 0x91
+ push rbp
+ push rsi
+ nop
+ push rsp
+ mov bl, 0x83
+ invalid
+ pop rcx
+ mov ebx, 0xcf58c4e3
+ mov ecx, [rax+0x20]
+ jbe 0x145
+ o16 js 0x94
+ xor ch, [rax-0x65]
+ sahf
+ or dil, [r14-0x243d2266]
+ and eax, 0x8134fcda
+ xchg [rdx], bh
+ mov al, 0xd0
+ xchg esp, eax
+ invalid
+ sub eax, 0xe7fb27a4
+ cmc
+ and eax, 0x7f5f47f6
+ jno 0x198
+ and dword [rsi-0x79], 0x84d0c980
+ cdq
+ div word [rdi-0x44]
+ sub bl, ch
+ push rsp
+ or [rcx-0x522c65b6], dl
+ jnp 0xea
+ movsd
+ sub al, 0xe0
+ wait
+ invalid
+ invalid
+ invalid
+ test al, 0x7b
+ int3
+ cmpsd
+ in al, 0xac
+ mov dl, 0xd8
+ push rsp
+ add edi, ecx
+ invalid
+ invalid
+ bswap ebp
+ sbb eax, 0x132463c4
+ sub [rcx-0x674b5c0b], al
+ fstp8 st1
+ or al, 0x40
+ out dx, eax
+ or [rcx-0x47], esp
+ jae 0x162
+ call 0xffffffff95858333
+ invalid
+ ficom dword [rcx]
+ movsb
+ invalid
+ mov al, 0x78
+ xor eax, 0x62526832
+ int1
+ or [rax-0x19702e11], cl
+ xchg ecx, eax
+ jns 0x112
+ pushfq
+ jb 0x1cd
+ ficom word [rsi]
+ invalid
+ invalid
+ loopnz 0x14f
+ push rax
+ xor [rax+0x2f], esp
+ cli
+ insd
+ invalid
+ jz 0x1d1
+ imul ebp, [rsi+0x3], 0x4cc67437
+ fbstp [rax]
+ ret 0x7e91
+ xor eax, 0x9d1189e
+ xchg edi, eax
+ sub eax, 0xe34fb563
+ adc dword [rdx+0x50], 0xbe
+ mov fs, [rsi]
+ sbb eax, 0x8507dfba
+ pop rsi
+ xchg [fs:rdi+0x772f0d6d], esi
+ movsb
+ invalid
+ pop rbx
+ add [rbx-0x3c2bb051], edx
+ add ebp, [rsi]
+ xor esi, [rbx+rdx*8-0x73]
+ xlatb
+ mov esp, 0x84e415b
+ invalid
+ iretd
+ and esi, [rbx+0x42]
+ int3
+ push rsi
+ sbb esp, [rdi]
+ jnz 0x222
+ mov edx, 0x27656695
+ xor dl, dl
+ outsb
+ shl dl, 1
+ pop rbp
+ invalid
+ sub [r14-0x9], r8d
+ call 0x2d044abe
+ ret 0xd5d9
+ loopnz 0x193
+ xchg ebx, eax
+ or edx, [rdx]
+ cld
+ jp 0x227
+ and r13b, r11b
+ invalid
+ retf
+ xchg ebp, eax
+ in eax, 0xf1
+ invalid
+ scasb
+ invalid
+ invalid
+ mov eax, [0xddd71ebe4f574d9e]
+ lodsb
+ xor al, 0xa3
+ xchg esp, eax
+ shl dword [rbp-0x4c633132], 0x48
+ invalid
+ test al, 0xdd
+ mov edi, 0x4ebbc7d3
+ movsb
+ or al, 0x7c
+ stosd
+ push rcx
+ jnp 0x22d
+ xor bl, [rcx-0x786caa4d]
+ ror byte [rdx-0x4f], 0xf2
+ xchg ebp, eax
+ lock push rbx
+ xchg ecx, eax
+ push rbp
+ invalid
+ or eax, 0xbcf5e5cb
+ ror dl, cl
+ mov al, [0xd37de9dbc81304ba]
+ adc edi, esp
+ std
+ xor [rsi], edi
+ out 0x9b, al
+ invalid
+ rol byte [rbp+rsi+0x33], 0x47
+ or al, 0x73
+ jle 0x1f9
+ push rax
+ mov [0xb14468fb5fa687e4], al
+ xor al, 0xf2
+ mov [0x287b5403d8ab4c3], eax
+ loop 0x267
+ fdiv st0, st0
+ lodsd
+ sahf
+ loopnz 0x2e6
+ pop rbp
+ mov [0xbf562ac34a3a6118], eax
+ xchg edx, eax
+ mov eax, [0xb5f0b3f7d9662e8f]
+ hlt
+ rcl byte [rax+rdi*8-0x3f], 1
+ xor [fs:rdi-0x2b], ch
+ lahf
+ push rbx
+ mov byte [rdi-0x712d8348], 0xac
+ retf 0xe411
+ sbb [rbp+rdx*8-0x1412e356], bl
+ mov [0x8f318a08bc346bfc], eax
+ pop rbp
+ invalid
+ add [rip+0x22efb4e4], edx
+ or cl, [rsi]
+ push rsp
+ movsxd edx, dword [rip-0x2b463dea]
+ sar [rcx+0x7d], cl
+ retf
+ invalid
+ mov ebx, 0x93818ee4
+ jg 0x2c9
+ loope 0x34f
+ shr dl, 0x87
+ invalid
+ xchg ecx, eax
+ adc [rdi-0x4a], dl
+ scasd
+ push qword [rdi-0x62c36b91]
+ scasd
+ in al, 0x1b
+ push rdi
+ fdiv qword [rcx+0x5f]
+ jae 0x2b6
+ jg 0x297
+ invalid
+ test eax, 0x9b7c0025
+ sub dword [rbx], 0xfe1c3c3d
+ mov ch, 0xec
+ cmpsd
+ jp 0x299
+ invalid
+ push rdi
+ xor [rdx+rcx*2+0x498841f], edi
+ mov ebp, 0xf0b2a7ed
+ jnp 0x35a
+ sbb [rdi-0x44], ecx
+ loope 0x392
+ add [rbp-0xfea7e27], ecx
+ movsb
+ hlt
+ movsb
+ invalid
+ sbb al, 0x2d
+ cmpsb
+ cwde
+ invalid
+ invalid
+ mov [0x313df81954c7e06f], eax
+ push rbp
+ push rsp
+ mov edi, 0x78579764
+ xor [rbp-0x45], bh
+ fnstsw word [rcx-0x7f]
+ invalid
+ shl dword [rcx], 0xe0
+ or esp, [rdi-0x2b2ad6da]
+ push rdi
+ movsxd ebx, dword [rdi+0x38ed8291]
+ in eax, dx
+ neg qword [rip+0x1d58c367]
+ stc
+ insd
+ mov cl, 0x34
+ mov dl, 0x1b
+ mov eax, [0x35867cbb0c33a1f8]
+ invalid
+ mov [rbx], al
+ invalid
+ out dx, al
+ lodsd
+ invalid
+ jnz 0x3b5
+ movsxd eax, edi
+ cmpsd
+ hlt
+ mov edi, 0x95ac2357
+ push rbp
+ pop r11
+ adc eax, 0x8ba88bc4
+ shr eax, cl
+ div byte [r9]
+ invalid
+ pop rcx
+ fstp9 st0
+ mov ebp, 0xa44b1a13
+ xor esi, [rsi-0x27]
+ sbb [rsi], edx
+ ror byte [rcx-0x44c143de], cl
+ outsd
+ and edi, [rsi-0x2aca0bcb]
+ scasd
+ add [rax], dh
+ js 0x3dc
+ invalid
+ and al, [rbp+0x23c5bfdf]
+ jge 0x3d9
+ xchg edi, eax
+ test [rcx+0x36], bl
+ xor eax, 0x2ef2dd51
+ mov esi, 0x6cdd5b1f
+ push rax
+ fstp qword [rax+0x7a564f77]
+ movsb
+ mov esp, 0x6edc8fdc
+ xor eax, 0x57e4a5d1
+ mov edi, 0x4890a0bc
+ fdivr st0, st2
+ popfq
+ jo 0x39f
+ invalid
+ nop
+ in eax, 0xe
+ in eax, 0xc1
+ cmp [rbp+rbx*2+0x1e18e69a], ah
+ xchg [rbx+0x514c44bd], ecx
+ invalid
+ cmpsd
+ outsd
+ stosd
+ wait
+ invalid
+ mov eax, 0xe426f49a
+ mov esi, 0x3d7db05c
+ and [rbx+0x34], esi
+ fisubr dword [rcx+0x9]
+ stosb
+ cmp [rdi-0x5f634764], cl
+ jg 0x44a
+ cmp [rsi+0x55f9b487], dh
+ fild qword [rdi+0x31]
+ pop rax
+ invalid
+ mov cl, 0x1f
+ clc
+ jns 0x442
+ mov ebp, [rdx]
+ in eax, 0x6
+ mov ah, 0x85
+ adc ecx, [rbx-0x1d]
+ jnp 0x3ed
+ xchg esp, eax
+ invalid
+ jg 0x491
+ invalid
+ adc al, 0x11
+ fidiv word [rbp+0x4b4154c3]
+ jle 0x3db
+ test [rbp+0x72685122], eax
+ not byte [rdx+0x50]
+ mov [0xe4e9f270ab3ad9be], al
+ add eax, 0x6f043646
+ mov [0x1d76ebadb9c99ce8], eax
+ shl dword [rcx-0x71f25365], 1
+ adc eax, 0xaddf2af1
+ and al, 0x52
+ mov cl, al
+ push rdx
+ and eax, 0xf6050662
+ in al, dx
+ push rsi
+ jmp 0x4f3
+ push rbx
+ cld
+ or al, 0xe4
+ jnz 0x4bd
+ shl byte [rax], 1
+ mov ecx, 0x10a2583c
+ mov esp, 0x8c1432da
+ jp 0x4af
+ invalid
+ jmp dword far [rbx-0x914d8eb]
+ int 0xbb
+ outsq
+ mov dl, 0x55
+ sbb al, 0xbb
+ xchg esp, eax
+ sbb eax, 0x6752a77e
+ and eax, 0xd7a1d401
+ test eax, 0xcacf5092
+ sar dword [rsi-0x77853110], 0xce
+ mov bh, 0xf7
+ and al, 0x80
+ cmp [rax+rdx*4], dh
+ in eax, 0xcf
+ xor [rsi], ch
+ scasd
+ cmp eax, 0x2b823c89
+ mov [rax], dh
+ mov esi, 0x59a0f5b9
+ jle 0x47f
+ hlt
+ invalid
+ movsb
+ lea esi, [rbx+0x33428281]
+ invalid
+ mov esp, 0x777cb8f
+ wait
+ repne push rsi
+ adc al, 0xb7
+ wait
+ cmp eax, 0x8468a78a
+ fstp qword [rdx-0x6816cfc0]
+ invalid
+ invalid
+ mov [0xd3b81bcb2d7023a1], eax
+ mov r12, 0xb4a79c363ab79fff
+ lodsd
+ or dh, [rdx]
+ invalid
+ xor [rcx], ecx
+ mov edi, 0xa1440147
+ cmp [rbx-0x1d], eax
+ mov dword [rsp+rsi*4-0x70], 0xb08aa420
+ xchg ebp, eax
+ sbb ebp, ebx
+ mov bl, 0x42
+ xchg [rbp-0x1f], edi
+ xor eax, 0x23062d90
+ lock add bl, [rbx+0x2]
+ popfq
+ leave
+ sar dword [rcx-0x61], 0x7d
+ jp 0x4f2
+ xchg ebx, eax
+ mov ecx, 0x76700e5d
+ fsub dword [rax+0x38de11eb]
+ scasd
+ stc
+ xchg esi, eax
+ mov al, [0x3429ddfb4efd36a2]
+ out 0xf6, eax
+ add eax, 0x28f76ccd
+ invalid
+ rep cmpsd
+ leave
+ pop rdi
+ jrcxz 0x52d
+ retf 0x3450
+ mov ch, ah
+ movsd
+ stosb
+ sti
+ or bl, [rbx+0x1ea54199]
+ mov al, [0x4a4f4d93383cc0d6]
+ add [rax], rcx
+ adc al, 0x6e
+ leave
+ adc al, 0x26
+ jmp 0x556
+ invalid
+ insd
+ invalid
+ invalid
+ and al, 0xc7
+ sub al, 0x77
+ or al, 0xae
+ xchg esp, eax
+ invalid
+ retf
+ repne cmp rax, 0x787cbcd0
+ cmp dh, bh
+ or edx, esi
+ jo 0x55b
+ xor al, 0x9b
+ test byte [rbp-0x428bfe9c], 0xe9
+ mov [0xb052f352d2e9e77a], eax
+ ja 0x57c
+ fidiv dword [rdx-0x6e519214]
+ rol bh, 1
+ and eax, 0x47c6ad88
+ cli
+ out 0x66, eax
+ ja 0x5f0
+ mov [0x73068a7ed24da31c], al
+ or eax, 0xd9133977
+ xchg ebx, eax
+ xlatb
+ cdq
+ invalid
+ sahf
+ mov ebx, 0xff345910
+ mov al, [0x83e8a61f5ec8f4c1]
+ invalid
+ invalid
+ jns 0x5b9
+ mov bl, 0x7a
+ adc esi, eax
+ invalid
+ hlt
+ and al, 0x3b
+ adc [rsi+rcx*8], dl
+ rep fstp qword [rax+0x23]
+ out dx, ax
+ jno 0x59b
+ imul esp, ebp, 0xfd
+ or [rbp-0x51bba45e], ah
+ jrcxz 0x5d4
+ cmp bh, ah
+ in eax, dx
+ invalid
+ nop
+ sbb al, 0xd8
+ invalid
+ jno 0x5ee
+ fdivr dword [rcx-0x4a]
+ popfq
+ invalid
+ pop rdi
+ in al, 0xa8
+ xchg ebx, eax
+ mov dh, 0x9f
+ invalid
+ out dx, eax
+ nop
+ test eax, 0x6ed9741d
+ mov eax, [0x2761c6f753344910]
+ invalid
+ out dx, eax
+ adc ebx, [rdx-0xd26b757]
+ sub al, 0x46
+ mov eax, 0x83fec441
+ mov cl, 0x9d
+ scasd
+ cmp esi, eax
+ sub [rdi-0x66], eax
+ invalid
+ sti
+ invalid
+ mov al, [0xcca5604125e6ebf3]
+ test al, 0xc0
+ mov cl, 0x39
+ insd
+ jmp 0x627
+ add eax, 0xda66295d
+ cmp [rdi+0x22], edi
+ push rax
+ sub al, 0x5e
+ sbb ecx, [rax]
+ xchg ecx, eax
+ out 0xe2, eax
+ pop rbx
+ jp 0x653
+ invalid
+ cmp ebp, [rdx+0x2c79fa79]
+ shl byte [rdx-0x46991cdb], 1
+ in al, dx
+ lodsd
+ insb
+ add eax, 0x4e2eb90b
+ cmp al, 0xfb
+ sub eax, 0x52f2a8d8
+ mov ecx, [rsi+0x8]
+ and ecx, [rax-0x46070bae]
+ fcom st0, st7
+ int1
+ mov esi, 0x700d5708
+ mov ebp, 0x678e58a1
+ adc esp, [rcx]
+ adc dword [rax], 0xbf
+ and dword [rsp+rdx*4], 0xc6
+ push rbx
+ sub eax, 0x9e1fa2af
+ mov ecx, 0xdcdf29ae
+ clc
+ cmp cl, cl
+ cmc
+ enter 0x4f3f, 0xf8
+ invalid
+ xchg edx, eax
+ jno 0x66e
+ jmp 0x699
+ loop 0x6ad
+ jz 0x66e
+ invalid
+ sbb edx, [rbx-0x18]
+ invalid
+ sub eax, [rsi+rbp*2-0x378f579e]
+ mov esp, 0xd4e71aab
+ or cl, [rip+0x1b1a3f6c]
+ in eax, 0x7c
+ sbb eax, 0xb9b94d07
+ insd
+ mov bl, 0x8a
+ push 0xf9
+ sbb ecx, [rax+0x1b31669e]
+ mov esi, 0xd1de5b3d
+ js 0x6fc
+ sbb eax, 0x6ffe0d5
+ jge 0x6c6
+ insb
+ ret 0xda6
+ mov esp, 0x39e9ba3b
+ xchg ecx, eax
+ jle 0x793
+ mov edx, 0x840bd8e3
+ mov dh, 0xd1
+ invalid
+ xor al, [rax+rcx*8-0x5fa220f]
+ adc ebx, eax
+ jle 0x7a4
+ jae 0x758
+ pop rsi
+ invalid
+ hlt
+ jbe 0x731
+ jge 0x78e
+ ret
+ in al, dx
+ lodsd
+ ja 0x74e
+ pop rbx
+ scasd
+ cld
+ mov bh, 0xa0
+ adc ah, [rax]
+ sbb al, 0x53
+ imul eax, [rcx-0x64f16c76], 0x53744fdc
+ cmpsb
+ xchg [rdx+0x64915082], ebp
+ imul byte [r10-0x5d]
+ lahf
+ add eax, 0x6086adde
+ or al, 0xfb
+ or eax, 0xa0926d7b
+ in eax, dx
+ in al, 0x36
+ jbe 0x73d
+ int1
+ xlatb
+ fidiv dword [rsi]
+ mov [rdi], dl
+ inc al
+ mov [rcx-0x67b89dad], esp
+ xlatb
+ mov edx, 0x54abea50
+ jo 0x7ae
+ add dh, [rdi]
+ fsub qword [rcx]
+ xor [rdi+rcx+0x48], ebp
+ lahf
+ movsxd ebp, dword [rdx-0x4b]
+ invalid
+ clc
+ mov esp, 0x9cbba834
+ std
+ jrcxz 0x7a0
+ add r13, [r15-0x40]
+ mov edx, 0x9717a522
+ sub [rsp+rdi*4], ch
+ lahf
+ mov esp, 0x47e94f18
+ xchg [ds:rsi], esi
+ pushfq
+ push rbp
+ cmp edx, [rdi]
+ jz 0x834
+ xchg esp, eax
+ invalid
+ push rcx
+ invalid
+ stc
+ inc byte [rdx+0x53fc8bf5]
+ sbb ah, [rsi+0xe069e65]
+ shr edx, cl
+ in al, dx
+ invalid
+ xchg esp, eax
+ and [rdx], ecx
+ wait
+ invalid
+ jle 0x779
+ invalid
+ mov [rcx-0x65], ah
+ invalid
+ jnp 0x7f4
+ jmp 0x731edc27
+ jns 0x796
+ mov cl, 0xba
+ xor eax, 0x5713d376
+ jp 0x87b
+ cmp eax, [rax-0x2a]
+ xor dword [rdi], 0xbe56b7cd
+ jns 0x80f
+ xchg edi, eax
+ in al, dx
+ ret 0xfc88
+ xchg esp, eax
+ outsd
+ mov ecx, 0xcb629fe0
+ outsd
+ popfq
+ push rsp
+ xchg ecx, eax
+ mov ecx, 0x3ff2b740
+ adc eax, 0xb4cf7f6a
+ movsxd ebx, dword [rsi-0x4442af85]
+ call dword far [rdi+0x63a461e9]
+ mov eax, [rbp+0x4d]
+ push rsi
+ invalid
+ or eax, [rbp-0x14]
+ push rsi
+ sbb eax, 0x3e8fc0ae
+ and al, [rdi-0x3b]
+ push rcx
+ invalid
+ xchg [rcx+0x6b], esp
+ fcmove st0, st4
+ invalid
+ xchg ebp, eax
+ xchg ebx, eax
+ push qword [rbx]
+ sub [rax], dl
+ clc
+ xor eax, 0xdc2ee2
+ add [rbx+0x55fcd786], eax
+ jg 0x88e
+ jmp 0xffffffff88ddccf9
+ pop rbp
+ cld
+ in al, dx
+ and ecx, [rsi-0xceb0903]
+ xor [rsi+0x8], al
+ fstp qword [rax-0x6e]
+ ja 0x803
+ invalid
+ sbb byte [rdi], 0x8a
+ out dx, eax
+ imul edx, [rdi-0x4a92ef92], 0x59
+ sub esi, [rip+0x2d7ff4e5]
+ stc
+ mov [rbx], ds
+ or dword [rsp+rbx*8], 0x63ee6442
+ invalid
+ push rax
+ invalid
+ fsubrp st5, st0
+ jl 0x909
+ loop 0x832
+ mov esp, 0x34beb4a6
+ adc eax, 0xc6745838
+ out 0x71, al
+ cmp ch, dl
+ sub ecx, [rdx+0x5c519127]
+ sbb [rdi+0x33ca5cc1], ecx
+ invalid
+ or eax, [rdx+0x0]
+ invalid
+ movsd
+ cmc
+ cmpsb
+ add [rbx+rax*4+0x11], ch
+ jz 0x848
+ and [rbp-0x2d], ebp
+ retf
+ sbb [rcx], dl
+ mov dh, 0x35
+ rcl dword [rdi-0x1f], cl
+ or [rax-0x38], dh
+ invalid
+ and [rax-0x2f], edi
+ mov cl, 0xc8
+ jrcxz 0x951
+ and eax, 0xe26682e6
+ sub al, dh
+ sub bh, [rax]
+ invalid
+ sbb dl, [rdx-0xaaaaf2d]
+ jbe 0x93a
+ leave
+ adc edx, [rbx]
+ mov cl, 0xbb
+ push rbx
+ and eax, [rax+0xa]
+ iretd
+ outsd
+ xor [rsi+0x10f4d0e8], edx
+ cmp eax, 0x1cf5d799
+ invalid
+ loop 0x8f9
+ jbe 0x937
+ and r13, r11
+ sbb al, [rax+0x2f880b12]
+ pop rdi
+ nop
+ xchg esp, eax
+ sti
+ invalid
+ movsxd esp, dword [rcx+0x31da1f77]
+ mov al, [0x58d87b9abdb8071b]
+ invalid
+ pop rdx
+ sub eax, 0xda173f5c
+ retf
+ and eax, 0x71674aa9
+ mov eax, [0x9bfd5c32310bed12]
+ invalid
+ xlatb
+ sub [rax], dil
+ jnz 0x8d3
+ invalid
+ and rdi, [rsi-0x5b56010f]
+ or ebx, [ss:rax+0x2d]
+ adc ebp, ebx
+ adc [rsi-0x6ae02dcb], ecx
+ mov [rsi+0x3f], eax
+ ja 0x957
+ sub esp, edx
+ xor dword [rdi], 0xa7
+ loop 0x936
+ std
+ mov bh, [rcx+0x46b49152]
+ in al, dx
+ mov dl, 0x45
+ xchg edx, eax
+ push 0xc5
+ wait
+ pushfq
+ sti
+ in al, dx
+ jge 0x901
+ jbe 0x9be
+ xchg edx, eax
+ xchg r10d, eax
+ cmp ch, cl
+ loop 0x9d3
+ lodsq
+ pop rbx
+ xchg [rdi-0x54b76ca0], ah
+ js 0x96e
+ mov ecx, 0xafdca604
+ stosd
+ invalid
+ adc esi, [rcx-0x51e827d8]
+ rcr byte [rbp+0x3a], 1
+ sub [rcx], eax
+ mov ebp, 0xffd342cb
+ and ah, ch
+ push rsp
+ loope 0x9b4
+ xor r10b, r11b
+ out dx, al
+ mov [rdi], esi
+ jl 0x982
+ invalid
+ fld qword [rbp-0x7c]
+ insd
+ wait
+ push r15
+ adc ebx, [rdx-0x27]
+ invalid
+ xor dword [rcx], 0x5c
+ dec byte [rsi-0x3f]
+ or [rdx], eax
+ xchg edx, eax
+ invalid
+ outsd
+ xor [rdi-0x7bceb489], edx
+ lea edx, [rcx+rbp*2-0xd]
+ mov edx, 0xbe94bcdf
+ mov ecx, 0x1314367e
+ invalid
+ lock shl byte [rbx], 0x56
+ mov [rsi+0x194b4c6c], ss
+ out 0xbb, al
+ sub ecx, eax
+ or al, 0xaf
+ jno 0xa19
+ invalid
+ popfq
+ xor [rcx+0x2d0988f6], esp
+ wait
+ mov eax, [0x9002615cbfbf9891]
+ add bl, [rbp+0x7c]
+ rcl edi, 0xe
+ iretd
+ std
+ int3
+ stosd
+ shl dword [rdx-0x34], 1
+ cmp dl, dh
+ jno 0xa01
+ adc dl, [rdx-0x5d8e538f]
+ invalid
+ push rcx
+ int3
+ invalid
+ pushfq
+ cmp ebp, ebx
+ jle 0x9e2
+ invalid
+ cmp [rdi+0x5f], ah
+ jle 0xa98
+ in al, 0x2f
+ adc [rbx], eax
+ idiv ebp
+ invalid
+ lea ebp, [rdx-0x6e]
+ pop r14
+ xor [rip+0x1aee8ce4], esp
+ jz 0xaa5
+ invalid
+ sahf
+ shl dword [rsi+0x47], 0xf0
+ movsd
+ rol dword [r9+0x1b142a6a], 1
+ int3
+ mov cl, 0x8a
+ lock repne cmp eax, ebp
+ mov [rsi+rbx*8], al
+ add al, 0x91
+ movsxd edx, dword [rdi]
+ jnz 0xa6c
+ invalid
+ adc ecx, [rdi+0x7a]
+ jp 0xa88
+ invalid
+ push rbx
+ mov [rbp-0x32], bh
+ or al, 0x23
+ iretd
+ psubusb mm7, mm4
+ jrcxz 0xaaf
+ invalid
+ invalid
+ xchg ebx, eax
+ mov dl, 0x8e
+ test al, 0xcd
+ invalid
+ adc al, 0x5b
+ sbb eax, 0x708660b
+ repne shl al, 0xf5
+ invalid
+ invalid
+ xchg ebx, eax
+ imul eax, [rbx], 0x59d49ea2
+ xchg ecx, eax
+ invalid
+ invalid
+ loopnz 0xa7e
+ jb 0xae5
+ and esp, esp
+ call 0xffffffffdd289080
+ jns 0xa40
+ invalid
+ mov al, 0xfc
+ invalid
+ jnz 0xa94
+ mov ecx, 0xbaf1b0a2
+ cmp [rbp+rdi*8-0x56cb209f], edx
+ cs movsb
+ in al, dx
+ mov ecx, 0x8ee46992
+ mov edx, 0xf73d610b
+ test [rbx+rbx], ebx
+ insd
+ mov ch, 0x66
+ sbb eax, [rdx-0x65c6cef9]
+ call 0xfffffffff9747199
+ btc [rcx], edi
+ invalid
+ jl 0xb20
+ jrcxz 0xb2f
+ scasd
+ cmpsb
+ lahf
+ invalid
+ add al, 0x97
+ pushfq
+ invalid
+ invalid
+ invalid
+ invalid
+ invalid
+ jb 0xaaf
+ cmpsd
+ sti
+ invalid
+ out dx, eax
+ mov [rdx+0x43], eax
+ xor eax, 0x604a48
+ fdiv qword [rbp-0x13]
+ cdq
+ and eax, 0xe70452e6
+ lahf
+ invalid
+ jz 0xb01
+ push rbx
+ or esp, [rbx-0x16]
+ fbstp [rdi]
+ xor dword [rsi+rsi+0x5a920d7f], 0xc38b1a72
+ invalid
+ rol dword [rax-0x8], 1
+ push dword 0xb5f787ab
+ cmp [rip-0x44816a06], ebp
+ test [r15+0x748ab13c], r12
+ invalid
+ and dl, [rsi]
+ xchg [rax+rax*8+0x366852ed], bh
+ pop rax
+ in eax, dx
+ stosb
+ popfq
+ cli
+ invalid
+ sub [rcx-0x26edeab7], ah
+ fisub dword [rdx]
+ pop rdi
+ sahf
+ std
+ jnp 0xafd
+ push dword 0x657c0db7
+ push rdi
+ invalid
+ int3
+ mov ch, 0xb4
+ adc eax, 0xfc744747
+ mov dh, 0x9b
+ jns 0xbcd
+ std
+ xor dh, al
+ push rdx
+ mov ebp, 0x95134ff4
+ xor ah, [rax+rcx*2]
+ jg 0xbab
+ invalid
+ test [rdx-0x156fc96c], ecx
+ rep lodsb
+ repne mov ecx, 0x793b9c9e
+ stc
+ stosd
+ invalid
+ invalid
+ sbb al, 0x4
+ mov [0x171fa672cbc2f994], al
+ sar dword [rip+0x44386b47], 0xbe
+ and bl, [rcx-0x7903995]
+ mov ch, 0x93
+ pop rdx
+ int 0x82
+ xchg edi, eax
+ mov bl, [rbx-0x56]
+ stosb
+ invalid
+ mov spl, 0x4d
+ or eax, [rdx-0x7592f5b1]
+ js 0xb49
+ or [rax+rsi+0x3f1aae4d], ecx
+ jp 0xb5b
+ movsd
+ outsb
+ nop
+ sub ecx, [rdx]
+ out dx, al
+ sub eax, [rdx]
+ stc
+ pop rdi
+ adc al, 0xbf
+ repne mov eax, [0xd8ee6375d45f0f35]
+ imul ebx, [rip+0x696e72bc], 0xe0
+ js 0xb9d
+ or [rax], ebp
+ invalid
+ lock and [rbx+0x55], ch
+ test al, 0xca
+ cmpsd
+ xor al, 0xdb
+ lock mov cl, bl
+ pop rbp
+ invalid
+ int 0xbc
+ add eax, 0x4e7026e7
+ mov bpl, 0x50
+ xlatb
+ test [rax+0x66e4487a], eax
+ or eax, 0xd31061f4
+ call 0xffffffffb945a135
+ invalid
+ jle 0xbde
+ pop rbx
+ or dword [rax+rdx*2], 0xd2e35a54
+ fisubr word [rdx]
+ popfq
+ out dx, eax
+ and [rsi], bh
+ mov ebx, 0x8089623
+ push rdx
+ jo 0xc82
+ xor ch, [rdx+0x4]
+ jb 0xc04
+ cmc
+ neg byte [rsi-0x53]
+ pop rdx
+ sbb al, 0x3f
+ invalid
+ mov ecx, 0xafa84356
+ nop
+ mov al, 0xb5
+ or byte [rax+0x71], 0x43
+ xchg edx, eax
+ invalid
+ movsxd ebx, dword [rdx-0x12d13e96]
+ invalid
+ out dx, al
+ adc eax, 0xa897a4b9
+ a32 jz 0xc46
+ movsb
+ imul esi, [rsi+0x53fbc5a1], 0x5a
+ jg 0xbda
+ invalid
+ invalid
+ jbe 0xc8c
+ lahf
+ jge 0xca9
+ imul edi, [rax], 0x2c4aa59b
+ sub [rbp+0x3e], bl
+ and ebx, [rcx-0x3177f2f8]
+ sub [rbp+0x11], r9d
+ pop rsp
+ push r13
+ invalid
+ mov ah, 0x36
+ jge 0xc35
+ jnp 0xcb2
+ pop rdx
+ or bpl, r8b
+ sub [rbx], ch
+ o16 jb 0xcf9
+ invalid
+ sub eax, 0xc6c32927
+ mov [0xcd93ee45e262d532], eax
+ cmp al, 0x63
+ mov ecx, 0xd89bdfe3
+ invalid
+ lock invalid
+ xchg al, ch
+ add eax, 0x359ed371
+ sub al, [rdi+0x6932c6c5]
+ jmp 0xc39
+ xlatb
+ invalid
+ xor dh, [rdi]
+ movsxd ecx, dword [rsp+rdi*2]
+ test al, 0x4e
+ fbld [rcx+rcx*2-0xd]
+ pop rax
+ pop rdi
+ add dword [rdi+0x56ca6c2a], 0x15
+ scasb
+ invalid
+ sbb eax, 0xa744404f
+ int 0x66
+ sbb [rsi], esi
+ and [rsi], esi
+ invalid
+ sub bh, cl
+ call 0xffffffffc8bd8c41
+ adc bl, [rsi]
+ stosd
+ jz 0xcf3
+ rol ah, 1
+ int1
+ mov bl, 0x4b
+ invalid
+ or al, 0xd5
+ imul ecx, [rdx+0x1c187bd3], 0x6f7bffe8
+ sbb edi, ebp
+ push rbx
+ test al, 0x4a
+ fidivr word [rbx-0x242b8d19]
+ mov [0x5752c397fa1e3ac4], eax
+ invalid
+ adc r8b, bpl
+ wait
+ cdq
+ out dx, al
+ test [rbx-0x27767354], ecx
+ fcom dword [rax-0x25]
+ stosb
+ lahf
+ a32 mov ebx, 0xeceb1d22
+ rcl byte [rcx-0x3356397a], 1
+ leave
+ and dh, [rdi+0x109fe867]
+ retf
+ mov edi, 0x7c84aa58
+ cld
+ cmp esp, ebx
+ xchg [rbx-0x6a], edx
+ invalid
+ mov cr1, [rbp+0x1b]
+ invalid
+ cli
+ xor ecx, [rax-0x23a33572]
+ jb 0xd25
+ imul ebx, ebx, 0x30976844
+ sbb eax, 0xd37c2cb
+ invalid
+ xor dword [rsi], 0x1db6cb00
+ mov cl, 0x2c
+ mov [rsi-0x6f], edi
+ leave
+ mov [rbx], bh
+ imul eax, [rsi], 0x894b630a
+ add eax, [rsi+0x65]
+ xchg edi, eax
+ sub edi, edx
+ repne or ebp, [rax-0x58]
+ loope 0xcfb
+ sub eax, 0x4b9f573e
+ lea edx, [rdi]
+ in al, 0x80
+ jae 0xd7d
+ xchg edi, eax
+ sbb al, 0x22
+ invalid
+ lahf
+ invalid
+ invalid
+ invalid
+ push rdx
+ jno 0xda6
+ invalid
+ ret 0xc7e4
+ invalid
+ fbld [rbx]
+ mov edi, 0x10ad479b
+ repne sahf
+ sbb ch, [rax+0x39b6e4c7]
+ fmul qword [rcx+0x7b14c8c2]
+ xchg edi, eax
+ int1
+ mov ebx, [rcx+rsi]
+ fxch7 st0
+ pop r15
+ popfq
+ xor eax, 0x78b5d870
+ mov esp, 0x72aa7c3b
+ cmp eax, 0xdca682af
+ invalid
+ shl dword [rsp+rbp-0xc], cl
+ std
+ xor al, 0x1d
+ or eax, 0x84135706
+ int1
+ invalid
+ out 0xfe, al
+ test byte [rax-0x6c], 0x2f
+ movsxd ebp, dword [rsi+0x37]
+ or al, 0xa8
+ xor [rdx], ah
+ xchg esi, eax
+ xchg ecx, eax
+ add [rdx+0x8], al
+ jl 0xdf6
+ ficom dword [rsi]
+ and byte [rcx], 0xbe
+ and al, 0xfd
+ test esi, esi
+ sub al, 0x33
+ int1
+ jbe 0xe3c
+ invalid
+ xor al, 0x89
+ mov ebp, 0x24ea9942
+ push rcx
+ jnz 0xddc
+ invalid
+ retf
+ scasb
+ invalid
+ mov [0xa334ad69764fda10], al
+ xor al, [rbp+0x1365310f]
+ add eax, 0x9236756a
+ mov bh, 0x9f
+ mov eax, 0xc973540d
+ xor eax, 0xd144f52
+ rol byte [rbp-0x3a6aaa95], 0x1f
+ jae 0xea7
+ xor [rsi+0x58], ebx
+ or bl, [rcx]
+ and ebx, [rdx-0x6]
+ test [rdi+0x4b2ab0c5], dh
+ and edi, [rcx-0x391bf36b]
+ stc
+ mov al, [0xd7717d234da547be]
+ lock jbe 0xec9
+ mov ch, 0xa9
+ cmp [rdx+0x52], esp
+ xor al, 0x22
+ invalid
+ sub dh, 0x45
+ sub eax, 0xb234d79d
+ mov bh, 0x55
+ mov ecx, 0x2e32c2c1
+ pop rax
+ or eax, [rbx+0xac8ed1]
+ invalid
+ sub eax, 0x894f5fde
+ push dword 0xe04e1ab1
+ stosd
+ out 0xbc, eax
+ pop rbp
+ and eax, 0x4f828d00
+ nop
+ push rbx
+ xor al, 0x20
+ jno 0xe8c
+ sbb dword [rbx+0x23ce924], 0xf8a9277e
+ mov dl, 0xb
+ fcomp3 st6
+ out dx, al
+ sub [rbx+0x2a1886ca], edx
+ ficomp dword [rcx+0x523e59e8]
+ cmp [rbx+rax*4], ebp
+ in al, 0xdc
+ pop rsi
+ not dword [rdx+0x49]
+ lodsb
+ in al, 0x43
+ invalid
+ mov [0xd5e59a5afc88276e], eax
+ mov ch, 0xef
+ repne mov [0xa3ec8cfa02217a9a], eax
+ ret 0xe676
+ xchg [rax-0x5d9acac6], dl
+ adc [rdi], esp
+ add dh, dl
+ cmpsd
+ ficomp dword [rcx+0x6393bcdf]
+ mov cl, 0x51
+ cli
+ popfq
+ invalid
+ push rbp
+ adc [rbp-0x6fbc7a8f], ah
+ add ebp, ebx
+ maskmovq mm2, [rax-0x17]
+ js 0xee5
+ mov dl, bh
+ push rdi
+ push rdi
+ shr eax, cl
+ or eax, 0x25e8312c
+ xchg ebx, eax
+ sbb al, 0x80
+ and esi, [rcx]
+ test al, 0x14
+ invalid
+ ret
+ adc [r14+0x3b], esp
+ invalid
+ cmp ebx, [rcx-0x34]
+ rol byte [rsi+0x477b9d74], cl
+ sbb eax, ebx
+ cdq
+ push rbx
+ invalid
+ ja 0xf88
+ invalid
+ adc eax, 0x35fd79c6
+ wait
+ xchg [rbp-0x6be506a5], ebp
+ fbld [rax-0x1cb9686a]
+ stosb
+ mov [rdx+0x22], cr0
+ xchg edi, eax
+ imul esi, edi, 0xa2b53f5f
+ push rax
+ cmp [rcx+rbp*4], esp
+ invalid
+ invalid
+ or esi, edi
+ loope 0xf83
+ outsd
+ call 0xffffffff96f1a13f
+ invalid
+ sti
+ mov ecx, 0x2bb9610f
+ lahf
+ and bh, [rbx+0x4bf49c08]
+ imul dword [rbx-0x19]
+ test al, 0x67
+ shl dword [rdx], 0x17
+ in eax, 0xfd
+ wait
+ cmp eax, 0x816f37f
+ adc [rax], ebp
+ push dword 0x844dd8cf
+ sub al, [rcx]
+ stosb
+ shr dword [rax+0x5a994de7], 0xd
+ mov r15d, 0x35e63e4c
+ cwde
+ add [rdi-0xa], ch
+ sub al, 0x99
+ jle 0xf79
+ push rsi
+ cmpsb
+ sub dword [fs:rax+0x68], 0x7ef16c89
+ xor [rsi-0x4e], dh
+ cmp al, 0xa4
+ ror byte [rsi+0x4d005502], 0x8
+ scasb
+ mul edi
+ invalid
+ out 0x11, al
+ or ah, [rdi+0x7ee5927a]
+ fxch4 st1
+ pop rcx
+ add al, 0x60
+ invalid
+ xor bl, [rbx+0x35f387ce]
+ add al, [rdi+0x1c8087e3]
+ sahf
+ sub esi, ecx
+ invalid
+ call 0x50247e10
+ popfq
+ pop rbp
+ int 0x92
+ rcl dword [rbp+0x19f7c430], 1
+ iretd
+ mov [0x13a0ab169814d961], al
+ out 0x29, al
+ xchg ebx, eax
+ sub bl, [rax]
+ idiv esi
+ sub eax, 0x8fd0971c
+ push rdx
+ sbb ecx, esp
+ retf 0x3ab0
+ xor al, 0x97
+ adc [rax], edi
+ jle 0xf8d
+ adc [rbx+0x12ac2e1d], edi
+ rcl ebx, 1
+ jnp 0xfa9
+ fist dword [rdi+rsi*8+0x61]
+ ja 0xfb0
+ scasd
+ push rax
+ mov esp, 0x4e0f5827
+ stc
+ invalid
+ jnp 0x1027
+ xchg esp, eax
+ push rbx
+ push rdi
+ jnz 0x105f
+ mov [0xa481572c929b4468], eax
+ mov dh, 0x56
+ xchg esi, eax
+ add cl, [rsi]
+ shr [rdx-0x75], cl
+ jno 0xfc1
+ clc
+ invalid
+ xchg ecx, eax
+ jmp 0x41fee261
+ invalid
+ cmp byte [rsp+rcx], 0xd0
+ pop rax
+ jp 0x1051
+ outsd
+ test al, 0x78
+ mov bh, 0xd3
+ out 0x69, eax
+ mov [0x315cf7d53a661122], al
+ invalid
+ mov cl, 0xcf
+ mov [r8], ds
+ mov [0xb3b880136689ce77], al
+ or [rbx-0x132ccee7], bl
+ js 0x1035
+ jmp 0x20210c31
+ invalid
+ cmpsd
+ jge 0x1090
+ mov [rdi+0x6445aac3], cr1
+ test [rax+0x57], ebp
+ push rax
+ in al, 0x10
+ int3
+ loope 0x1051
+ jns 0x1054
+ call 0xffffffff8df4850a
+ mov ah, 0x7c
+ sar dword [rdx+rax], 1
+ mov esi, 0x2ededbe8
+ rol dword [rbx+0x1d65e59b], 0x60
+ scasd
+ mov cl, 0xe0
+ or [rcx-0x6d], rdi
+ invalid
+ add al, 0x7c
+ invalid
+ adc esp, 0x5101715
+ jnz 0x1089
+ sbb al, 0x4d
+ or r12b, [r10]
+ push dword 0x4c073002
+ o16 cld
+ sbb [fs:rsi], bl
+ ja 0x103c
+ pop rbp
+ push rbp
+ retf 0xb295
+ push rsi
+ lfs edx, [rbp-0x22f7e3a7]
+ mov [rax+0xa8511d4], cl
+ invalid
+ retf
+ iretd
+ invalid
+ jmp 0x1082
+ mov [0x319a974ae3814005], eax
+ hlt
+ push rsi
+ cwde
+ stosb
+ lock stosd
+ push rsi
+ or eax, 0x5769a868
+ fnstenv [rbx+rax*2+0x3a]
+ fmul qword [rdx-0x76]
+ invalid
+ pop rbp
+ jle 0x10a3
+ pop rbx
+ adc eax, 0x90e1b11f
+ out dx, eax
+ xchg esp, eax
+ cmpsq
+ xchg esi, eax
+ sub edi, ebp
+ imul byte [rdi+0x90a85bb]
+ rcl ebx, 1
+ mov esi, 0x2e7eab26
+ loopnz 0x10eb
+ jae 0x1180
+ clc
+ out 0x76, al
+ pop rax
+ loop 0x1137
+ mov [0xb52e4e13044d0fdf], al
+ fmulp st2, st0
+ fild word [rdx]
+ in eax, dx
+ loopnz 0x10ad
+ and dl, [rbp+0x28]
+ invalid
+ cmp [rax*4-0x99ed375], dl
+ movsd
+ lodsd
+ cmp eax, [rdx-0x6ab441ee]
+ push rax
+ int1
+ lodsd
+ jo 0x110b
+ pop rsi
+ push rdx
+ mov al, ah
+ iretd
+ push rbp
+ add eax, 0x3014be2a
+ xchg ecx, eax
+ cmp esi, [rcx+0x8]
+ ret 0x6b83
+ mov dh, 0xbe
+ insb
+ movsxd ecx, dword [rdx]
+ and [rdi], edx
+ clc
+ loope 0x10e3
+ rep cdq
+ invalid
+ jnp 0x110f
+ sbb eax, 0x9a64c8f1
+ mov bh, 0x98
+ sub [rdi-0x2617e54f], edx
+ invalid
+ push rcx
+ mov [0x579790fbb884f280], eax
+ js 0x117e
+ repne insb
+ rcpps xmm4, xmm7
+ fstp qword [rip+0x67acc747]
+ add edx, [rcx-0x756dfb0e]
+ invalid
+ invalid
+ push rbp
+ sbb [rsi+rcx*8], bh
+ popfq
+ rcr byte [rbp-0x24], 1
+ jns 0x113f
+ adc esp, [rip+0x449f06e8]
+ mov esp, 0x81827652
+ std
+ leave
+ invalid
+ invalid
+ invalid
+ mov ecx, 0x83ba4d00
+ cmc
+ sbb eax, 0x4233b376
+ pop rbp
+ invalid
+ invalid
+ repne rcl dword [rax], 0x25
+ invalid
+ jb 0x11db
+ test al, 0xb6
+ lodsd
+ loope 0x11f6
+ invalid
+ jrcxz 0x11fb
+ xlatb
+ push rsp
+ rol dword [rdi], 0x91
+ mov cl, [rdi+0x7c227c17]
+ mov [0xfc12f1bf4ab6de35], eax
+ retf
+ or al, 0xe5
+ and al, 0xe3
+ std
+ mov [rdi+rsi*2-0x1653644a], cr0
+ mov eax, [0x4eeffe24f6a896cb]
+ pushfq
+ xchg ebp, eax
+ xchg esi, eax
+ xor cl, [rbx]
+ adc dword [rdx], 0x1d
+ push 0x1b
+ out dx, eax
+ xor eax, 0xead77ae7
+ ret
+ or [rdx], ch
+ invalid
+ pop rdx
+ jb 0x11da
+ or bl, r15b
+ lahf
+ call 0x7374fe67
+ or [rax+0x1e], edx
+ in eax, dx
+ jmp 0x1252
+ push dword 0x44fc27c4
+ sahf
+ invalid
+ int 0x97
+ invalid
+ int1
+ add eax, 0x2db9f27a
+ sbb rsp, rdi
+ invalid
+ cmp eax, ebp
+ jmp 0x11e8
+ mov al, [0x15e1c01d899bd4d5]
+ mov dh, 0x2a
+ mov cl, 0x25
+ loop 0x127f
+ invalid
+ and dword [rcx-0x76], 0xb99f8636
+ test [rcx-0x384456bd], cl
+ xor [rdi-0x3d], dl
+ sbb eax, [rax]
+ xchg [rdx], bl
+ mov [0x8436cf4ab0c392e], al
+ pop rsp
+ pop rax
+ sahf
+ out dx, al
+ mov [0x6ea05a4fe52d324f], eax
+ xor eax, edi
+ stosd
+ test [rdx], bh
+ shr dword [rdi], 1
+ fadd st1, st0
+ fidivr word [r13-0x2d]
+ pop rsp
+ mov ecx, ss
+ out dx, eax
+ invalid
+ add al, 0xb6
+ jo 0x1276
+ shr word [rcx], 1
+ invalid
+ push rbp
+ retf 0x8a07
+ neg byte [rsi+0x2e311678]
+ invalid
+ ror dword [rdi+0x7d1712ae], 1
+ pop rbp
+ cmp al, 0xd6
+ shr byte [rcx-0x76], 0xab
+ jae 0x1317
+ adc eax, esi
+ mov bl, 0x2a
+ mov al, [0x671a6c7401efe9cf]
+ mov fs, [rsi-0x226df648]
+ add eax, [rcx+rbp*2+0x74b3d204]
+ adc [rcx+0x5874d0e7], esi
+ invalid
+ mov dh, 0x99
+ push rsi
+ lodsd
+ insb
+ rep int 0xc5
+ imul esi, [rsi-0x2be7450c], 0xdc3e6aa9
+ mov al, [0x6219c9da14f5a367]
+ pushfq
+ cmp eax, 0x3f7b46d1
+ invalid
+ xchg ebx, eax
+ std
+ out dx, al
+ in al, 0x2d
+ sub [rcx+rbp*4+0x3257ed1b], ecx
+ hlt
+ retf 0x52a7
+ invalid
+ clc
+ jp 0x1372
+ pop rcx
+ mov ch, 0x16
+ pop rdi
+ movsd
+ mov al, [0xd61f8da50f676f88]
+ invalid
+ add cl, bh
+ invalid
+ ret
+ invalid
+ mov edi, 0x9aa0bc93
+ fst qword [rbp-0x60]
+ xor ch, [rcx-0xc]
+ o16 jl 0x131b
+ int1
+ jg 0x134d
+ pop rbx
+ invalid
+ cmp al, 0x16
+ and ecx, ecx
+ push rsp
+ invalid
+ sti
+ mov eax, [0xf5d91b3a2e5f2e6d]
+ a32 outsd
+ invalid
+ fidivr word [r15+0x19a7fbfd]
+ invalid
+ invalid
+ in eax, 0x3a
+ invalid
+ imul esp, [rbp-0x4dd25066], 0xf9b49a78
+ invalid
+ popfq
+ mov al, [0xa6e05ab6eb9452f2]
+ or [rip-0x36e0ce0f], ch
+ sbb eax, ebp
+ outsb
+ invalid
+ invalid
+ mov ebx, 0xd15a3fdb
+ and ebp, ebx
+ movsb
+ cmpsd
+ invalid
+ not dword [rax+rdx*8+0x469f8f3]
+ xchg [rsi], r12
+ sbb [rcx+0x6f], esi
+ pop rax
+ invalid
+ mov fs, [rax-0x30292aa4]
+ movsxd esp, dword [rdx+0x4d]
+ mov dl, dh
+ scasd
+ xlatb
+ sub bl, [rax-0x322ad67b]
+ mov eax, [0x35653e659a135194]
+ pop rdi
+ out dx, eax
+ invalid
+ invalid
+ push rax
+ mov ss, ebp
+ insb
+ and byte [rbp+rax*4-0x54], 0x9f
+ push rsp
+ mov esp, 0xe5950f68
+ mov al, [0xdd71f2ad9dfefe12]
+ jb 0x13ca
+ xlatb
+ or [rbx], esp
+ invalid
+ jp 0x1370
+ call dword far [rdx+rcx*8-0x65be806a]
+ mov esi, 0xe6ba140e
+ loope 0x135f
+ int1
+ add dl, bl
+ shl dword [rdx], cl
+ cmp ah, bh
+ adc eax, 0x6ce8b335
+ shr cl, 1
+ fst dword [ss:rbp+0x1548eb37]
+ adc al, 0x16
+ mov dword [rsi], 0x9b74e96e
+ mov al, [0xecffe0bdd7d81053]
+ test eax, 0xf072c923
+ invalid
+ cdq
+ scasd
+ push 0xa3
+ movsd
+ jno 0x13fa
+ int1
+ popfq
+ ret 0x7d8
+ mov ax, 0x3b54
+ imul esp, [rcx], 0x49ee5bc3
+ pop rsp
+ and eax, 0x910ef28a
+ xchg rsi, rax
+ stc
+ jle 0x143a
+ jmp 0x13c2
+ test [rip-0x32d0b32c], ebp
+ mov esi, 0xa806610a
+ fnstcw word [rax-0x1eddbe6b]
+ xchg edx, eax
+ cmpsd
+ push rsi
+ sbb [rax+rdi*4], ebp
+ leave
+ fld dword [rdx-0x5aa8bc63]
+ mov ecx, [rdi+0x582c6389]
+ test eax, 0x22d7aebd
+ js 0x1429
+ sar dword [rdx+0x4f332cec], 0xdf
+ xor cl, ah
+ mov [0xa401424c9c31a845], al
+ xor esi, esp
+ mov edx, 0x8d76fdff
+ cmp edi, [rcx+0x55843717]
+ xchg ebx, eax
+ enter 0xd9ab, 0xfc
+ rcl byte [rbp+0x3f], cl
+ adc [rdx-0x7cb0224d], eax
+ sub al, 0x3a
+ mov al, [0x75ce4221c6bb70d2]
+ pop r12
+ or [rcx-0x61], ch
+ sub bh, 0xe4
+ out 0xe3, al
+ mov ah, ah
+ cmp cl, bl
+ xchg ebp, eax
+ js 0x14e2
+ add eax, 0x647dbe38
+ sahf
+ xchg ebx, eax
+ loope 0x14dd
+ popfq
+ mov al, [0x3b3c3b3d7f296e05]
+ sub [rax+rdi*4], ch
+ wait
+ xchg ebx, eax
+ and [rcx], esi
+ mov ecx, 0x26b9bfa3
+ mov ah, 0xe
+ invalid
+ loope 0x1543
+ push rbp
+ movsb
+ lock sbb al, 0x1a
+ jl 0x14ad
+ sub al, 0x21
+ test [rbx], dl
+ add eax, esi
+ insd
+ cmc
+ xor eax, 0x58f5af66
+ enter 0xa7, 0xa9
+ or dword [rdx], 0xba
+ mov ebx, 0xe87ff0ca
+ invalid
+ pop rsi
+ imul r15, [r15+rbp], 0xe5f147d2
+ ja 0x14e1
+ and al, 0xf7
+ stosd
+ and [rax-0x5ff04554], ah
+ push rsi
+ jnz 0x14bc
+ jz 0x1540
+ invalid
+ mov al, [fs:0x77cac247f9978476]
+ adc eax, 0xf17e329d
+ mov ch, 0xad
+ repne fisub word [rcx]
+ mov bh, 0x95
+ scasd
+ mov ebp, 0xe42974fa
+ shl dword [cs:rax+0x7d], 0xb5
+ invalid
+ adc ch, [rdi-0x28]
+ in eax, dx
+ fcom qword [rcx-0x57]
+ cwde
+ invalid
+ push rdx
+ jg 0x1583
+ cqo
+ invalid
+ inc byte [rsp]
+ or ah, ch
+ invalid
+ lea esp, [rdx]
+ mov esi, 0x22fa717f
+ lock mov dh, 0x1d
+ jb 0x14ca
+ sub eax, 0xe4721f1d
+ out dx, al
+ wait
+ adc al, [rcx+0x7e159d2e]
+ xchg [rax+0x59], cl
+ retf 0xd5f8
+ lock mov ah, al
+ lahf
+ mov [0x11e645a8394bf5ea], al
+ fidivr dword [rbx]
+ cmp esp, esp
+ xor al, 0x1
+ lahf
+ pop rax
+ sbb ebp, [rcx]
+ pop rsp
+ jmp 0x15a1
+ adc [rax-0x517d3357], edi
+ mov ebx, 0x4081775a
+ push rcx
+ and dh, [rdi+0x167a0a1c]
+ invalid
+ invalid
+ or al, 0x84
+ cmp eax, 0x9ca782ad
+ xchg [rdx+0x2], ecx
+ add [rcx+0xda06ed7], ch
+ or [rcx+0x155f52cb], dl
+ invalid
+ sub eax, 0x5c5c79e3
+ push rbx
+ movsxd ebp, dword [rdi+rcx*4]
+ jns 0x1558
+ mov r8, 0xea11d2a8a9a984a2
+ mov bh, [rsi]
+ xor dl, al
+ xchg [rdx], dh
+ o16 mov ah, 0xc3
+ wait
+ add [rbx-0x4], cl
+ repne iretd
+ xor dh, [rax]
+ outsb
+ mov [rbx], gs
+ leave
+ add edx, ebx
+ push r10
+ ret
+ sub al, 0x73
+ jz 0x15c4
+ jz 0x15e1
+ imul dword [rcx-0x39bdc9f9]
+ movsd
+ pop rdi
+ std
+ adc eax, 0xa9a370cb
+ fdivr qword [rdi]
+ and ah, 0xe2
+ stosd
+ invalid
+ jg 0x15dc
+ movsb
+ test edi, esp
+ adc dil, r11b
+ a32 jmp 0x3f9e287b
+ int3
+ jp 0x1619
+ in eax, 0xad
+ rcr dword [rdi+0x7cc0d60a], 1
+ invalid
+ cmc
+ adc edx, ebp
+ mov al, dl
+ sub bh, [rbp-0x6c7934fc]
+ sbb [rcx+0x6], edi
+ adc al, 0xe4
+ invalid
+ mov bl, 0x1e
+ rcr dword [rax-0x5b], 0x13
+ invalid
+ and eax, 0xf37ffe65
+ push rdi
+ xchg edx, eax
+ and eax, 0x23999b38
+ rcl byte [rip+0x1181eca], 0x2f
+ cmpsb
+ invalid
+ std
+ and dh, [rax-0x52]
+ or [rsi-0x2595882a], bh
+ xor esi, [rbp-0x33]
+ jno 0x1612
+ hlt
+ clc
+ invalid
+ adc ah, 0xaf
+ invalid
+ mov [0xeabb59a06ed1dcaf], al
+ push rsi
+ cmp ebx, ebp
+ fnstenv [rdx-0x6e8e7abc]
+ sbb eax, 0xc47a9a29
+ lea ebp, [rdx]
+ popfq
+ jno 0x1626
+ in al, 0x9e
+ push rsi
+ a32 hlt
+ invalid
+ mov [0x1efcc893905effe7], al
+ call rsp
+ mov edx, 0xa5e99ee0
+ invalid
+ push dword 0x67ec8548
+ pop rbp
+ cmp ah, [rdi+0x30]
+ out 0xe6, al
+ sub eax, [rsi]
+ invalid
+ jge 0x16b3
+ clc
+ adc byte [ds:rdx-0x1e], 0x3e
+ rep fstp qword [rdi]
+ push rcx
+ xchg esi, eax
+ test al, 0x96
+ stc
+ jz 0x1661
+ mov esi, 0x49cfb604
+ or eax, 0x6ea9445e
+ push 0x77
+ loop 0x1662
+ invalid
+ xchg edi, eax
+ invalid
+ invalid
+ invalid
+ cmp eax, 0xce5632a8
+ xor [rdx], dl
+ xchg ebp, eax
+ xor al, 0x70
+ mul byte [rbx]
+ shl dword [rbp+0x13], 0x62
+ scasb
+ invalid
+ ja 0x1689
+ outsd
+ xchg edx, eax
+ push rbx
+ out 0xd9, al
+ o16 xor bl, [rbx]
+ int1
+ imul ebp, [rsi+0x6418118], 0xbb5f1483
+ sub edx, [rip+0x3ec270c7]
+ xor al, 0xc
+ iretd
+ lahf
+ invalid
+ retf 0x474
+ jo 0x168a
+ cmp dl, [rbp+0x439b5eb5]
+ int1
+ invalid
+ mov dh, 0x82
+ mov dh, [rcx-0x42c7efe8]
+ nop
+ and al, 0xda
+ ja 0x1710
+ mov al, [0x8c8dc84c074e37a2]
+ sub eax, 0x9e2cad87
+ test dword [rsi+0x5e], 0xa79f92d7
+ xor edi, [rdi+rbx*4+0x35]
+ mov ah, 0xef
+ xchg [rdi-0x74], ah
+ pop rsp
+ fisub dword [rax+0x5f7e69a0]
+ adc [rbp+0x56], ch
+ jno 0x177c
+ mov esp, 0xe148d095
+ ret 0x5abf
+ or byte [rax-0x7cbb461e], 0xa1
+ mov edx, 0x793024a1
+ out dx, al
+ add eax, 0x38760464
+ ret 0xf750
+ mov eax, [rbp+0x22334ef8]
+ invalid
+ sbb edx, [rdx+0x62a36164]
+ pop rsi
+ retf 0x78ab
+ push rsi
+ stosb
+ or [rdi], ebp
+ or ch, [rsi+rsi*8+0x67]
+ std
+ jae 0x172e
+ test dword [rdi-0x76], 0x4d148686
+ sti
+ pop rdx
+ fs lodsb
+ cmc
+ add [rip+0x9ad6f4f], ecx
+ hlt
+ adc ecx, eax
+ mov bl, ch
+ invalid
+ imul ebx, [rbx+rsi*8+0x3b], 0x27
+ loop 0x1765
+ int1
+ or eax, 0x723b6a7b
+ pop rbp
+ call 0x61e56998
+ int3
+ sbb edx, [rsi]
+ popfq
+ movsb
+ fcom dword [rdx]
+ rcr dword [rbp-0x1babaa55], cl
+ test ebp, 0x9be65a09
+ adc [rdx], eax
+ out dx, al
+ ficom word [rbp+0x36]
+ imul ebp
+ invalid
+ mov esi, 0x422b9112
+ or edx, eax
+ xchg [rsi+0x5571090b], bl
+ invalid
+ outsb
+ jg 0x17f2
+ cmpsd
+ mov esp, 0x3fb40b93
+ cmpsd
+ xchg esp, eax
+ movsb
+ mov esp, 0xdac30464
+ rep pushfq
+ or al, 0x20
+ mov esi, 0x2a8c97b2
+ imul edx, esp, 0xbb0ca76e
+ js 0x17b6
+ jz 0x17eb
+ jmp dword far [rcx-0xa]
+ mov eax, [0x9d9f7676a1397eef]
+ mov [0xa095e9a85b35f5c8], eax
+ test eax, 0xc8bd7b3e
+ mov [0x85ab25798d841f77], eax
+ or eax, [rbx]
+ lodsd
+ sub [rcx-0x6f667f15], edx
+ imul esp, [rip-0x6ca30574], 0xc4
+ ret
+ insb
+ xor ch, [rdi]
+ retf 0xd0d4
+ nop
+ mov esi, 0x856de28d
+ sahf
+ movsxd esp, dword [rsi-0x5ef00d55]
+ invalid
+ mov cl, 0x0
+ adc al, 0x6c
+ retf
+ invalid
+ invalid
+ push 0xe6
+ jb 0x183d
+ jmp 0x180e
+ sar al, 0xef
+ loopnz 0x17e6
+ or eax, ebp
+ int3
+ dec byte [rbx-0x2d]
+ stosb
+ wait
+ sub [rdi-0xf51f6de], dl
+ xor eax, 0x4a765e6
+ insd
+ pop rax
+ xchg ebp, eax
+ pushfq
+ pop rbp
+ and eax, 0xdc381f2
+ shl esp, 0x76
+ push rax
+ or [rip-0x5726b0b2], cl
+ scasb
+ cmp al, 0x68
+ pop rsp
+ scasd
+ add [rip+0x737676eb], dh
+ adc [rbp+0xf4a7402], bl
+ mov al, 0xde
+ out 0x4d, eax
+ mov ebx, [rdx+0xa5c12fe]
+ jae 0x18f9
+ sahf
+ xlatb
+ scasb
+ hlt
+ mov ecx, 0x457d4b74
+ out dx, al
+ jns 0x18eb
+ cmc
+ movsxd edi, dword [rdi]
+ sbb eax, 0x20250ec9
+ xchg ecx, eax
+ mov edi, 0x43b176c7
+ iretd
+ invalid
+ invalid
+ out 0x9c, al
+ std
+ pop rsp
+ xor al, 0x91
+ push rbx
+ shr [rax], cl
+ mov [0x470aec75f35bbb75], eax
+ xor esp, edi
+ invalid
+ rol eax, cl
+ test [rbx+0x3f], dl
+ push rdi
+ and eax, 0x32b2babb
+ push rsi
+ out 0x5e, eax
+ jo 0x1932
+ outsd
+ stc
+ push rsi
+ loop 0x18e2
+ sub [rdx-0x1228c2fe], eax
+ and [rax+0x4f821eb9], edi
+ xchg edx, eax
+ invalid
+ jp 0x18f2
+ invalid
+ jnz 0x1910
+ rol byte [rdx-0x6bac1aca], 0x4f
+ jae 0x18e3
+ xchg ebx, eax
+ pop rdi
+ out 0x95, eax
+ invalid
+ nop
+ ret 0x476e
+ iretd
+ sar dword [rdx-0x78b760dd], cl
+ invalid
+ test [rax+0x5fc8a2c2], bh
+ pop rdi
+ out dx, al
+ jno 0x18b4
+ and al, 0xa1
+ xchg edx, eax
+ invalid
+ xchg ebx, eax
+ wait
+ jz 0x197a
+ fild dword [rcx+0xc009371]
+ sub ecx, [rax+0x7979f270]
+ mov edi, ecx
+ invalid
+ mov [rax+0x5cc0975], cs
+ sti
+ mov ecx, 0x1dcf877a
+ fild word [rbp-0x6d]
+ in al, 0xb7
+ clc
+ push rax
+ xor ecx, [0x410073a]
+ rcl dword [rdx-0x5331545a], cl
+ pop rsi
+ jnp 0x19a4
+ push dword 0x80472ab8
+ adc [rcx-0x3ebc4fc2], dh
+ pop rax
+ push rsp
+ push dword 0x6d340323
+ out dx, al
+ mov esp, 0x1c36e32
+ xor ebp, [rdi+0xe]
+ mov esi, 0x4c42f9c7
+ xor eax, 0xd6340960
+ invalid
+ pop rsp
+ add [rbx+rcx*8], ecx
+ cmp eax, 0x32b1191a
+ sbb r10b, [rax+0x4537a12c]
+ cwde
+ mov ecx, 0xc38677a
+ cmp [rax+0x61fcb9a5], dh
+ sbb [rsi-0x5cdc8b98], ebx
+ cmp eax, [rdx+0x4e]
+ jz 0x19f0
+ loop 0x195c
+ cmp bh, [rip+0x480f5d21]
+ add cl, [rcx+rbp*4-0x1d]
+ invalid
+ mov cl, cl
+ mov [rsp+rbx-0x298651cb], ecx
+ in eax, dx
+ xor [rbx+0x2f], ch
+ invalid
+ invalid
+ test [rsi-0x5db17f2e], bh
+ outsd
+ stosb
+ add [fs:rax], dl
+ stosb
+ jno 0x19a1
+ movsxd ecx, dword [rsi+0x57]
+ invalid
+ mov al, 0xd4
+ sub edi, eax
+ retf 0x3e58
+ cmp [rsi-0x1e], edx
+ sti
+ outsb
+ xchg esp, eax
+ loope 0x1a4d
+ jp 0x1a3b
+ invalid
+ sbb al, 0xf
+ invalid
+ invalid
+ retf 0xbf6c
+ mov dh, al
+ mov ebx, [rbp+0x30fd636f]
+ pop rbp
+ xor bh, cl
+ mov [rdx-0x6d], ch
+ xchg ecx, eax
+ sti
+ sar dword [rcx+0x40], cl
+ mov ebx, 0x1a7e9f97
+ a32 sti
+ add [rsi], al
+ pop rbp
+ fcmovb st0, st2
+ shl dword [rdx-0x34], 1
+ push rdx
+ push rdi
+ push rsi
+ push rsi
+ jmp qword near [rdx+rsi+0x78110a68]
+ sbb ebx, eax
+ ror byte [rdi-0x38], 1
+ shl dword [rbx], cl
+ call dword far [rcx+rdx*2-0x41f3f709]
+ cmp byte [rbx*4-0x6d860638], 0x49
+ jo 0x1a4f
+ lodsb
+ or al, 0xca
+ invalid
+ stosb
+ jg 0x1aaa
+ pushfq
+ invalid
+ test [rsi+0x43], cl
+ neg dword [r11+rbp*8+0x4]
+ stosd
+ mov esp, 0x40475c82
+ insd
+ or [rax+rdx*8-0x2b65d9a4], al
+ invalid
+ invalid
+ xchg ecx, eax
+ pop rsi
+ nop
+ pop rsp
+ cmp [rsi-0x38159f6b], ah
+ fcmovb st0, st1
+ xchg ecx, eax
+ pop rcx
+ pushfq
+ o16 cmc
+ call 0xffffffff8ce66f4d
+ mov r11b, 0xc9
+ invalid
+ jo 0x1ac9
+ fcomi st0, st5
+ repne outsb
+ invalid
+ or bh, [rax+0x39]
+ sub ah, [rax]
+ mov dl, 0xb3
+ sub al, 0x98
+ push rdx
+ mov [rax+0xe], ah
+ shl [rdi+0x6eb5866c], cl
+ js 0x1aab
+ movsb
+ xchg esp, eax
+ cmp al, 0x46
+ mov eax, [0xb8fbde058568d8a4]
+ invalid
+ mov al, 0xa
+ jo 0x1b05
+ xor ebx, esp
+ invalid
+ js 0x1a86
+ nop
+ pushfq
+ jnz 0x1ae9
+ push rsi
+ retf 0x694b
+ rcl byte [rdx-0x56], cl
+ out dx, al
+ scasd
+ invalid
+ jg 0x1ab8
+ sahf
+ imul edx, [rax+0x6ddee1d1], 0xbec11bee
+ sbb [rdi+0x39], bh
+ mov al, [0x40299b4e984c8f12]
+ mov eax, 0x13aa826
+ mov bl, 0x79
+ ja 0x1a9d
+ cwde
+ jmp 0xfffffffff3e40cd7
+ mov edx, 0x31d63c22
+ invalid
+ adc al, 0x17
+ jz 0x1b23
+ mov ebx, 0xc379989d
+ fmul dword [rdi]
+ mov [rbx-0x35], edx
+ jle 0x1ac1
+ lodsd
+ invalid
+ iretd
+ mov [rdx+0x781582cd], ch
+ or edi, [rdx]
+ add dword [ds:rdx+rcx-0x4dba991f], 0x4e
+ add dl, [rax-0x30031a9b]
+ invalid
+ jae 0x1ad4
+ invalid
+ imul ebx, [rbx], 0xb2
+ out 0x5d, al
+ xchg [rbx-0x217febf0], bh
+ int1
+ cmp al, 0x91
+ mov edx, [rcx+0x46]
+ sbb al, 0x68
+ outsb
+ adc al, 0x91
+ mov al, 0x9
+ jmp 0xfffffffff0b2372c
+ call qword near [rdx]
+ add eax, 0x1b448cbb
+ invalid
+ mov ch, 0x79
+ out 0xca, eax
+ mov edx, 0x8ab07a67
+ invalid
+ push rcx
+ shr edi, 0xb7
+ xor [rbx], edx
+ pop rsp
+ mov cr1, eax
+ shl dword [rcx-0x79b01cfc], cl
+ and [rip+0x5e540579], ebx
+ out 0xe2, eax
+ xor dh, [rsi+0x7a]
+ add al, 0xa3
+ invalid
+ out 0x50, al
+ std
+ invalid
+ xchg [cs:rcx-0x1fdc4003], bh
+ add [rbp+0x13c88cdb], ch
+ fnstenv [rcx-0x694abe77]
+ sbb ah, cl
+ xchg edi, eax
+ adc cl, ch
+ in al, 0x61
+ jrcxz 0x1b3f
+ movsd
+ mov edi, 0xfba7b96
+ xchg ebp, eax
+ and rax, 0xf98baabd
+ fidivr word [rbx-0x65]
+ adc [rbx-0x509d2ad6], cl
+ invalid
+ js 0x1b68
+ test al, 0x15
+ sti
+ stosb
+ or dh, ch
+ fldenv [rip-0x7abb7547]
+ in al, dx
+ add bh, [rbx+0x665b4789]
+ mov [rdi], dh
+ mov esi, 0xa21f773b
+ sbb eax, [rbx-0xb]
+ invalid
+ invalid
+ push rsi
+ cmp eax, 0x68b484b6
+ pop rsi
+ cmp al, 0x52
+ sbb bl, [rbx+0x3a]
+ mov esp, 0xaed65363
+ mov eax, 0x5e63d139
+ mov dh, 0xe9
+ outsb
+ repne sbb [rax], cx
+ scasd
+ invalid
+ adc dword [rbp-0x7ba8b8f0], 0x48c539c1
+ hlt
+ repne xchg [rsi+rax*2-0x54], bl
+ or eax, 0xd8650c5e
+ jnz 0x1bd7
+ cmp bl, bh
+ or [rcx-0x28], ecx
+ ret 0xd22c
+ invalid
+ pop rdi
+ scasb
+ xchg [rbp+0x7], ecx
+ invalid
+ movsb
+ ret
+ jl 0x1bde
+ pop rdx
+ std
+ mov ebp, 0xab4c7bf4
+ invalid
+ xor al, 0x7a
+ ret 0xf29c
+ invalid
+ sub [rsi+0x6687ba93], esp
+ push rsp
+ mov dl, 0xbb
+ fldenv [rsi]
+ sbb al, 0xa1
+ fstp tword [rbp-0xa682773]
+ cmpsd
+ mov al, 0x3f
+ in al, dx
+ cli
+ xchg esp, eax
+ mov edi, 0xb30543cb
+ pop rbx
+ rcr dword [rbx+0x30], 0x67
+ sub dh, [rbp+0x1d]
+ pop rdi
+ test [rbx+0x6e], ch
+ xchg [rbx+0x657aa8b5], r12d
+ invalid
+ and byte [rcx+0x703156eb], 0xb5
+ sbb ch, [rip+0x16860c65]
+ cmp [rax-0x1d], edx
+ mov es, [rdx+0x25cbccdb]
+ xor [ss:rax+0x2c97cfd0], esp
+ cmc
+ loop 0x1c87
+ loopnz 0x1c57
+ jnp 0x1c40
+ invalid
+ neg dword [rbx+0x156d414b]
+ nop
+ invalid
+ loopnz 0x1bfc
+ movsb
+ invalid
+ pop rbp
+ out 0x5c, eax
+ invalid
+ invalid
+ push rdi
+ adc edi, edx
+ sbb eax, [rbp-0x72ccc8fc]
+ mov es, edx
+ int 0x30
+ outsd
+ mov eax, [0x750e2be16de489de]
+ int3
+ invalid
+ jge 0x1c94
+ add eax, 0x3dba2e6
+ cmp dh, ch
+ mov rdi, 0x77705d6d63c90f79
+ nop [rdi+0x65]
+ jz 0x1cdc
+ adc cl, ah
+ invalid
+ invalid
+ mov [0x19d6cf93d7b4ab26], al
+ invalid
+ in al, 0x2c
+ pop rcx
+ pop rbx
+ rep insd
+ scasd
+ invalid
+ invalid
+ mov ebp, 0xc6c9b707
+ jp 0x1c6b
+ xlatb
+ out dx, eax
+ retf
+ and al, 0x70
+ push rbp
+ invalid
+ pop rdi
+ cmp eax, 0x67917e82
+ or esp, ebx
+ retf
+ in al, 0x3a
+ jno 0x1d19
+ cmp [rcx-0x47], bh
+ in al, 0x35
+ mov eax, 0x5264b9bd
+ push rsp
+ jo 0x1d1e
+ mov spl, 0x89
+ rol dword [rax-0x65], cl
+ in eax, 0x2d
+ mov ah, 0x36
+ invalid
+ sti
+ push rdx
+ invalid
+ shr byte [rsp+rcx-0x3b24763], 0xb
+ invalid
+ sbb dl, [rdi-0x4c0e59c9]
+ xor al, 0x89
+ int 0x35
+ sahf
+ out 0x81, eax
+ invalid
+ lock sti
+ xchg ecx, eax
+ retf
+ invalid
+ in al, dx
+ jmp 0xffffffffdbe510b0
+ push rcx
+ jno 0x1cd3
+ fldcw word [rsi+0x12d2c7bf]
+ bswap eax
+ mov edi, 0xd7354899
+ invalid
+ mov edi, 0xb0641f98
+ pop rbx
+ invalid
+ ror byte [rsi], 0xed
+ or ebx, esi
+ fdivr dword [rdi+0x25]
+ xchg [rcx+rax*8-0x47], al
+ sub [rip-0x3218f81], ecx
+ jae 0x1d67
+ jae 0x1d5c
+ wait
+ cmpsd
+ invalid
+ mov edx, 0x8dbce596
+ jle 0x1d8a
+ iretd
+ std
+ lodsb
+ sbb [rdx+0x206cc62b], ebp
+ invalid
+ pushfq
+ jmp 0x1d3e
+ invalid
+ invalid
+ mov edi, 0x82cd3871
+ mov edx, 0xb24f9fa6
+ sbb dword [rdi+0x3d7a8375], 0x7f3dbb4b
+ lea esi, [rbx+0xb]
+ sub al, 0x7b
+ o16 ja 0x1dc3
+ sar edi, 0xf
+ cdq
+ cwde
+ mov eax, [0x4902a7b6776c0b6c]
+ jle 0x1dee
+ mov ch, [rax]
+ and edx, esi
+ scasb
+ fcom2 st7
+ fstp qword [rax+rdx*8]
+ lodsb
+ push rsp
+ jnz 0x1d35
+ out dx, al
+ wait
+ adc ch, [rbx+0x56d5937d]
+ test eax, 0x54713fe4
+ loopnz 0x1d6b
+ xor eax, [rbp+0x72fd7a5e]
+ jmp 0x1dc4
+ in al, 0xfd
+ invalid
+ a32 mov eax, 0x3c9c07ca
+ invalid
+ fisttp qword [rcx-0x3d]
+ and bl, al
+ mov ebx, gs
+ xor [rdi], esi
+ invalid
+ push rcx
+ cdq
+ mov dl, 0x83
+ int1
+ ret 0xb54
+ out dx, al
+ cmp al, 0x92
+ xchg esi, eax
+ sbb dh, cl
+ mov ebx, [rdx-0x49]
+ invalid
+ xlatb
+ lodsb
+ imul ebp, [rax-0x5a6bfcd5], 0x18
+ nop
+ int1
+ loopnz 0x1df9
+ mov r9b, 0x1a
+ mov ch, al
+ jae 0x1df6
+ push rdi
+ sub al, 0xe4
+ or ah, bl
+ xchg ebx, eax
+ invalid
+ fsub qword [rdx-0x46]
+ out 0xd4, al
+ xor al, ah
+ int3
+ jp 0x1e4e
+ and ecx, esi
+ call 0x31131af9
+ pop rdx
+ outsd
+ invalid
+ or [rax+0x4b45f86], edx
+ cmp [rbx-0x13], al
+ ja 0x1e05
+ pop rsp
+ jbe 0x1e31
+ jge 0x1e1a
+ enter 0x1445, 0xe4
+ invalid
+ jl 0x1dd4
+ pop rsi
+ nop
+ jle 0x1e76
+ invalid
+ ja 0x1ea5
+ ja 0x1e29
+ or [rbx], ecx
+ invalid
+ movsd
+ xor dl, al
+ add byte [rdi], 0x83
+ repne jmp 0x1dc9
+ jmp 0xffffffffe25d2049
+ mov edx, [rdx+0x25]
+ mov dl, 0xfe
+ pop rsi
+ int1
+ test ebp, edi
+ jmp 0x1e47
+ movsd
+ mov edi, 0x3acb210b
+ jo 0x1e45
+ mov ah, 0x1d
+ and [rax+rdx+0x37], bh
+ out dx, al
+ invalid
--- /dev/null
+[bits 16]
+ movzx eax, word [bx]
--- /dev/null
+[bits 32]
+ mov [0x1000], bx
+ mov [0x10], ax
+ mov ax, [0x10]
+ mov byte [bx+si], 0x10
+ mov byte [bx+si+0x10], 0x10
+ mov word [bp+0x0], 0x10
+ mov word [bp+di+0x10], 0x10
+ mov dword [si+0x10], 0x10
+ mov word [di+0x10], 0x10
+ mov dword [bx+0x10], 0x1000
+ mov word [bx+0x1000], 0x1000
+ mov dword [ebx+ecx*4], 0x100
+ mov [eax+eax*2], eax
+ mov [edx+esi*8], ebp
+ mov dword [ecx*4+0x0], 0x100
+ mov byte [cs:0x100000], 0x10
+ mov word [eax+0x10], 0x10
+ mov [eax+0x10], ax
+ mov [eax+0x1000], ebx
+ mov [ebp+eax+0x0], esi
+ mov [ebp+edi+0x100000], esp
+ mov byte [esp], 0x10
+ add al, 0x10
+ add eax, ebx
+ push es
+ pop es
+ adc eax, 0x10000
+ and [eax], al
+ daa
+ inc ax
+ inc edx
+ push eax
+ push ax
+ pushad
+ bound eax, [eax]
+ bound ax, [ecx]
+ bsr ax, ax
+ bsf eax, [bx+si]
+ bswap eax
+ bt [eax], ax
+ btr ax, 0x10
+ btc ebx, 0x10
+ bts word [ebx], 0x10
+ call ax
+ call word near [bx+si]
+ call eax
+ call dword near [eax+ecx]
+ call word 0x10:0x100
+ call dword 0x10:0x10000
+ call word far [eax]
+ call dword far [bp+si]
+ cbw
+ cwd
+ clc
+ cld
+ clflush [eax]
+ cmp eax, ebx
+ cmp ecx, [bx]
+ cmpsb
+ cmpsw
+ cmpsd
+ cmpxchg [eax], ax
+ cmpxchg8b [ebx]
+ cpuid
+ das
+ inc eax
+ inc word [ecx]
+ dec byte [si]
+ in al, 0x10
+ in ax, 0x10
+ in eax, 0x10
+ insb
+ insw
+ insd
+ int 0x10
+ into
+ lahf
+ lds ax, [eax]
+ les eax, [ebx]
+ lea ax, [eax]
+ lea eax, [bx+si]
+ leave
+ lodsb
+ lodsw
+ lodsd
+ test al, bl
+ test [eax], bl
+ test [eax], ebx
+ test [eax], bx
+ ret
+ ret 0x10
+ aad 0x10
+ aam 0x10
+ salc
+ hlt
+ cmc
+ lock xchg ebx, eax
+ repne mov eax, ebx
+ rep mov eax, 0x10
+ push cs
+ outsd
+ outsw
+ mov ax, es
+ mov bx, ds
+ mov [eax], es
+ mov [ebx+ecx], cs
+ mov cs, [ebx+ecx]
+ wait
+ pushfw
+ pushfd
+ lodsw
+ lodsd
+ retf 0x10
+ int3
+ into
+ iretw
+ iretd
+ lar eax, [eax]
+ lsl ax, [bx]
+ syscall
+ clts
+ sysret
+ movups xmm0, xmm1
+ mov dr0, eax
+ wrmsr
+ rdmsr
+ rdtsc
+ rdtscp
+ rdpmc
+ sysenter
+ sysexit
+ cmovo eax, [eax]
+ cmovno eax, [bx]
+ cmovb eax, [eax]
+ cmovae eax, [bx]
+ cmovo eax, [eax]
+ cmovz eax, ebx
+ cmovnz eax, [eax]
+ cmovbe eax, [bx]
+ cmova eax, [bx]
+ movmskps eax, xmm0
+ movmskpd eax, xmm0
+ sqrtps xmm1, xmm0
+ rsqrtps xmm1, xmm0
+ rcpps xmm1, xmm0
+ andps xmm1, xmm0
+ orps xmm1, xmm0
+ xorps xmm1, xmm0
+ andnps xmm1, xmm0
+ sqrtss xmm1, xmm0
+ rsqrtss xmm1, xmm0
+ rcpss xmm1, xmm0
+ sqrtpd xmm1, xmm0
+ andpd xmm1, xmm0
+ andnpd xmm1, xmm0
+ orpd xmm1, xmm0
+ xorpd xmm1, xmm0
+ sqrtsd xmm1, xmm0
+ punpcklbw mm0, [eax]
+ punpcklwd mm0, mm1
+ punpckldq mm0, mm1
+ packsswb mm0, mm1
+ packsswb mm0, mm1
+ pcmpgtb mm0, mm1
+ pcmpgtw mm0, mm1
+ pcmpgtd mm0, mm1
+ packuswb mm0, mm1
+ punpcklbw xmm0, [eax]
+ punpcklwd xmm0, xmm1
+ punpckldq xmm0, xmm1
+ packsswb xmm0, xmm1
+ packsswb xmm0, xmm1
+ pcmpgtb xmm0, xmm1
+ pcmpgtw xmm0, xmm1
+ pcmpgtd xmm0, xmm1
+ packuswb xmm0, xmm1
+ pshufw mm0, mm1, 0x10
+ pcmpeqb mm0, mm1
+ pcmpeqw mm0, mm1
+ pcmpeqd mm0, mm1
+ pcmpeqb xmm0, xmm1
+ pcmpeqw xmm0, xmm1
+ pcmpeqd xmm0, xmm1
+ emms
+ pshufhw xmm0, xmm1, 0x10
+ pshufd xmm0, xmm1, 0x10
+ pshuflw xmm0, xmm1, 0x10
+ seto [eax]
+ setno [bx]
+ setz [es:eax+ecx*2+0x100]
+ push fs
+ pop fs
+ cpuid
+ bt [eax], eax
+ shld eax, ebx, 0x10
+ shld [eax], bx, cl
+ cmpxchg [eax], eax
+ lss eax, [eax]
+ btr [eax], eax
+ movnti [eax], eax
+ psrlw mm0, 0x10
+ fadd dword [eax]
+ imul eax, [eax], 0xf6
+ movd dword [eax], xmm0
+ movzx eax, word [eax]
+ push word [0x10]
+ insw
+ insd
+ fnstsw ax
+ fucomip st0, st1
+ fcomip st0, st7
+ fucomp st4
+ fucom st5
+ fstp st3
+ fst st1
+ ffree st0
+ fdiv st7, st0
+ fdivr st2, st0
+ fsub st4, st0
+ fsubr st6, st0
+ fmul st0, st0
+ fadd st5, st0
+ ficom word [eax]
+ fidivr word [eax]
+ fimul word [ebx]
+ fisub word [ecx]
+ fld qword [bx+si]
+ fisttp qword [edx+0x100]
+ fnstsw word [eax]
+ frstor [ebx]
+ prefetch [bx+si]
+ psrlq xmm0, 0x10
+ psrldq xmm0, 0x10
+ movsldup xmm0, [eax]
+ add [0xffffffff], eax
+ cvtsi2ss xmm1, dword [eax]
+ pause
+ pop dword [eax]
+ out 0x0, al
+ lldt [0x100]
+ lgdt [0x221]
+ sldt [0x233]
+ sgdt [0x443]
+ lidt [eax+0x333]
+ lldt ax
+ ltr bx
+ verr cx
+ verw dx
+ sldt ax
+ str bx
+ str eax
+ and esp, 0xfc
+ psrlw xmm1, 0x10
+ psraw xmm7, 0x1
+ psllw xmm2, 0x23
+ fldenv [0x10]
+ fldenv [0x123]
+ fldcw word [0x100]
+ fnstcw word [0x10]
+ ficom word [eax+ebx+0x10]
+ fstp tword [0x10]
+ fadd qword [eax+ebx*2+0x1]
+ frstor [0x100]
+ fnstsw word [0x100]
+ fiadd word [0x100]
+ fild word [0x10]
+ monitor
+ mwait
+ lfence
+ mfence
+ sfence
+ vmrun
+ vmmcall
+ vmload
+ vmsave
+ stgi
+ clgi
+ skinit
+ invlpga
--- /dev/null
+[bits 64]
+ mov rax, 0x102030405060708
+ mov [eax+0x10], ax
+ mov [eax+0x1000], ebx
+ mov [ebp+eax+0x0], esi
+ mov qword [ebp+edi+0x1000], 0x10
+ mov byte [esp], 0x10
+ mov [eax], rax
+ mov [r12], eax
+ mov [r13+r12+0x0], eax
+ mov [r8*4+0x0], sil
+ inc rax
+ dec rax
+ mov [rip+0x200], rax
+ mov rax, 0x10000
+ push rax
+ push r12
+ call word near [r8]
+ call qword near [rax]
+ call word far [r8]
+ call dword far [rax]
+ cbw
+ cwde
+ cdqe
+ cwd
+ cdq
+ cqo
+ cmovl rax, [rax]
+ cmovge eax, [rax]
+ clflush [r14]
+ cmp [rax], rax
+ cmp rbx, r12
+ cmp r12d, r8d
+ cmpsb
+ cmpsw
+ cmpsd
+ cmpsq
+ cmpxchg [eax], r14
+ cmpxchg8b [ebx]
+ inc r12d
+ inc dword [rax]
+ dec r11w
+ hlt
+ imul rax, [eax+ebx*8+0x100000], 0x10
+ idiv dword [r12]
+ enter 0x100, 0x0
+ enter 0x100, 0x1
+ enter 0x100, 0x10
+ in al, 0x10
+ in ax, 0x10
+ in eax, 0x10
+ lfs eax, [eax]
+ lgs eax, [ebx]
+ lea eax, [rbx]
+ lea r11, [eax]
+ lodsb
+ lodsq
+ lodsd
+ push rax
+ push r11
+ xchg [eax], sil
+ xchg [eax], ebx
+ xchg [eax], bx
+ xchg r8, rax
+ xchg r9, rax
+ xchg cx, ax
+ movsd
+ movsq
+ mov al, r11b
+ mov sil, al
+ mov r11b, dil
+ ret 0x10
+ pop rax
+ pop r11
+ pop qword [eax]
+ insd
+ outsd
+ mov [r14d], cs
+ mov cs, [ebx+ecx]
+ pushfq
+ scasq
+ lar rax, [eax]
+ lsl ax, [rbx]
+ movups xmm0, [r12d]
+ movupd xmm0, [r12d]
+ movsldup xmm0, [r12d]
+ movups xmm0, xmm1
+ movups xmm10, xmm12
+ movups xmm0, xmm12
+ movlps xmm0, [rax]
+ movlps [rax], xmm0
+ unpcklps xmm4, xmm5
+ unpckhps xmm4, xmm5
+ movhps xmm3, [eax]
+ movhps [rax], xmm3
+ movss xmm0, [eax]
+ movss [eax], xmm0
+ movlpd [eax], xmm0
+ movlpd xmm0, [eax]
+ unpcklpd xmm2, xmm4
+ unpckhpd xmm3, [eax+ebx*8+0xffffffff]
+ movhpd xmm3, [rax]
+ movhpd [rax], xmm2
+ movsd xmm3, xmm4
+ movddup xmm3, [rax]
+ mov dr0, rax
+ mov rax, dr1
+ movnti [eax], eax
+ movnti [rax], rax
+ movd dword [eax], xmm0
+ movd qword [eax], xmm0
+ movd xmm11, qword [eax]
+ vmmcall
+ vmrun
+ clgi
+ stgi
+ mfence
+ lfence
+ sfence
+ clflush [rax]
+ mov cr8, rax
+ push qword [eax]
+ push word [eax]
+ add bh, bh
+ add dil, dil
+ add sil, bpl
+ add al, sil
+ add rax, r12
+ add eax, r12d
+ prefetcht0 [eax]
+ prefetchnta [eax]
+ prefetch [eax]
+ add [r8], r9b
+ mov [rax-0x1], eax
+ inc rax
+ jmp qword near [eax]
+ jmp rax
+ mov [0x10], rax
+ mov rax, [0x10]
+ mov rax, 0x102030405060708
+ nop
+ xchg r8, rax
+ push ax
+ push rax
+ push r11
+ mov rax, [0x100]
+ pmovmskb r12d, xmm14
+ movdq2q mm0, xmm13
+ psrlw xmm10, 0x10
+ psraw xmm7, 0x1
+ psllw xmm12, 0x23
+ swapgs
+ fadd dword [rax+rbx]
+ shl rsi, 1
--- /dev/null
+[bits 64]
+
+ jnz near x
+ jo near x
+ jno word x
+ jc near x
+ jnc word x
+ jae dword x
+ jcxz x
+ jecxz x
+ jrcxz x
+ jmp near x
+ call x
+ jmp word x
+ jmp dword x
+ jmp word [eax]
+x: jmp qword [rax]
--- /dev/null
+0000000000000000 0f853b000000 jnz dword 0x41
+0000000000000006 0f8035000000 jo dword 0x41
+000000000000000c 660f813000 jno word 0x41
+0000000000000011 0f822a000000 jb dword 0x41
+0000000000000017 660f832500 jae word 0x41
+000000000000001c 0f831f000000 jae dword 0x41
+0000000000000022 67e31c jecxz 0x41
+0000000000000025 67e319 jecxz 0x41
+0000000000000028 e317 jrcxz 0x41
+000000000000002a e912000000 jmp 0x41
+000000000000002f e80d000000 call 0x41
+0000000000000034 66e90900 jmp 0x41
+0000000000000038 e904000000 jmp 0x41
+000000000000003d 6766ff20 jmp word near [eax]
+0000000000000041 ff20 jmp qword near [rax]
--- /dev/null
+
+ db 0xd1, 0xf6 ; shl Ev, 0x1
+ db 0xd0, 0xf6 ; shl Eb, 0x1
+ db 0xd9, 0xd9 ; fstp1 st1
+ db 0xdc, 0xd0 ; fcom2
+ db 0xdc, 0xd8 ; fcomp3
+ db 0xdd, 0xc8 ; fxch4
+ db 0xde, 0xd1 ; fcomp5
+ db 0xdf, 0xc3 ; fxch7
+ db 0xdf, 0xd0 ; fstp8
+ db 0xdf, 0xd8 ; fstp9
+
--- /dev/null
+ shl esi, 1
+ shl dh, 1
+ fstp1 st1
+ fcom2 st0
+ fcomp3 st0
+ fxch4 st0
+ fcomp5 st1
+ ffreep st3
+ fstp8 st0
+ fstp9 st0
--- /dev/null
+bin_PROGRAMS = udcli
+udcli_SOURCES = udcli.c
+udcli_CFLAGS = -I$(top_srcdir)/libudis86 -I$(top_srcdir)
+udcli_LDADD = ../libudis86/libudis86.la
--- /dev/null
+#
+# Makefile for win32 compilers
+# (I need some help here!)
+
+CC = cl
+CFLAGS = -O2
+RM = del
+
+
+.SUFFIXES: .c .obj
+
+.c.obj:
+ $(CC) -c $(CFLAGS) -o $@ $<
+
+OBJS = udcli.obj ../libudis86/udis86.lib
+
+udcli: $(OBJS)
+ $(CC) $(OBJS) -o udcli.exe
+
+clean:
+ $(RM) *.obj udcli.exe
--- /dev/null
+/* udis86 - udcli/udcli.c
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+#include <udis86.h>
+#include <config.h>
+
+#if defined(__amd64__) || defined(__x86_64__)
+# define FMT "l"
+#else
+# define FMT "ll"
+#endif
+
+#if defined(__DJGPP__) || defined(_WIN32)
+# include <io.h>
+# include <fcntl.h>
+#endif
+
+#ifdef __DJGPP__
+# include <unistd.h> /* for isatty() */
+# define _setmode setmode
+# define _fileno fileno
+# define _O_BINARY O_BINARY
+#endif
+
+/* help string */
+static char help[] =
+{
+ "Usage: %s [-option[s]] file\n"
+ "Options:\n"
+ " -16 : Set the disassembly mode to 16 bits. \n"
+ " -32 : Set the disassembly mode to 32 bits. (default)\n"
+ " -64 : Set the disassembly mode to 64 bits.\n"
+ " -intel : Set the output to INTEL (NASM like) syntax. (default)\n"
+ " -att : Set the output to AT&T (GAS like) syntax.\n"
+ " -v <v> : Set vendor. <v> = {intel, amd}.\n"
+ " -o <pc> : Set the value of program counter to <pc>. (default = 0)\n"
+ " -s <n> : Set the number of bytes to skip before disassembly to <n>.\n"
+ " -c <n> : Set the number of bytes to disassemble to <n>.\n"
+ " -x : Set the input mode to whitespace seperated 8-bit numbers in\n"
+ " hexadecimal representation. Example: 0f 01 ae 00\n"
+ " -noff : Do not display the offset of instructions.\n"
+ " -nohex : Do not display the hexadecimal code of instructions.\n"
+ " -h : Display this help message.\n"
+ " --version: Show version.\n"
+ "\n"
+ "Udcli is a front-end to the Udis86 Disassembler Library.\n"
+ "http://udis86.sourceforge.net/\n"
+};
+
+FILE* fptr = NULL;
+uint64_t o_skip = 0;
+uint64_t o_count = 0;
+unsigned char o_do_count= 0;
+unsigned char o_do_off = 1;
+unsigned char o_do_hex = 1;
+unsigned char o_do_x = 0;
+unsigned o_vendor = UD_VENDOR_AMD;
+
+int input_hook_x(ud_t* u);
+int input_hook_file(ud_t* u);
+
+int main(int argc, char **argv)
+{
+ char *prog_path = *argv;
+ char *s;
+ ud_t ud_obj;
+ int mode = 0;
+
+ /* initialize */
+ ud_init(&ud_obj);
+ ud_set_mode(&ud_obj, 32);
+ ud_set_syntax(&ud_obj, UD_SYN_INTEL);
+
+#ifdef __DJGPP__
+ if ( !isatty( fileno( stdin ) ) )
+#endif
+#if defined(__DJGPP) || defined(_WIN32)
+ _setmode(_fileno(stdin), _O_BINARY);
+#endif
+
+ fptr = stdin;
+
+ argv++;
+
+ /* loop through the args */
+ while(--argc > 0) {
+ if (strcmp(*argv,"-16") == 0) {
+ ud_set_mode(&ud_obj, 16);
+ mode = 16;
+ } else if (strcmp(*argv,"-32") == 0) {
+ ud_set_mode(&ud_obj, 32);
+ mode = 32;
+ } else if (strcmp(*argv,"-64") == 0) {
+ ud_set_mode(&ud_obj, 64);
+ mode = 64;
+ } else if (strcmp(*argv,"-intel") == 0)
+ ud_set_syntax(&ud_obj, UD_SYN_INTEL);
+ else if (strcmp(*argv,"-att") == 0)
+ ud_set_syntax(&ud_obj, UD_SYN_ATT);
+ else if (strcmp(*argv,"-noff") == 0)
+ o_do_off = 0;
+ else if (strcmp(*argv,"-nohex") == 0)
+ o_do_hex = 0;
+ else if (strcmp(*argv,"-x") == 0)
+ o_do_x = 1;
+ else if (strcmp(*argv,"-s") == 0)
+ if (--argc) {
+ s = *(++argv);
+ if (sscanf(s, "%" FMT "d", &o_skip) == 0)
+ fprintf(stderr, "Invalid value given for -s.\n");
+ } else {
+ fprintf(stderr, "No value given for -s.\n");
+ printf(help, prog_path);
+ exit(EXIT_FAILURE);
+ }
+ else if (strcmp(*argv,"-c") == 0)
+ if (--argc) {
+ o_do_count= 1;
+ s = *(++argv);
+ if (sscanf(s, "%" FMT "d", &o_count) == 0)
+ fprintf(stderr, "Invalid value given for -c.\n");
+ } else {
+ fprintf(stderr, "No value given for -c.\n");
+ printf(help, prog_path);
+ exit(EXIT_FAILURE);
+ }
+ else if (strcmp(*argv,"-v") == 0)
+ if (--argc) {
+ s = *(++argv);
+ if (*s == 'i')
+ ud_set_vendor(&ud_obj, UD_VENDOR_INTEL);
+ } else {
+ fprintf(stderr, "No value given for -v.\n");
+ printf(help, prog_path);
+ exit(EXIT_FAILURE);
+ }
+ else if (strcmp(*argv,"-o") == 0) {
+ if (--argc) {
+ uint64_t pc = 0;
+ s = *(++argv);
+ if (sscanf(s, "%" FMT "x", &pc) == 0)
+ fprintf(stderr, "Invalid value given for -o.\n");
+ ud_set_pc(&ud_obj, pc);
+ } else {
+ fprintf(stderr, "No value given for -o.\n");
+ printf(help, prog_path);
+ exit(EXIT_FAILURE);
+ }
+ } else if ( strcmp( *argv, "--version" ) == 0 ) {
+ fprintf(stderr, "%s\n", PACKAGE_STRING );
+ exit(0);
+ } else if((*argv)[0] == '-') {
+ fprintf(stderr, "Invalid option %s.\n", *argv);
+ printf(help, prog_path);
+ exit(EXIT_FAILURE);
+ } else {
+ static int i = 0;
+ s = *argv;
+ if (i) {
+ fprintf(stderr, "Multiple files specified.\n");
+ exit(EXIT_FAILURE);
+ } else i = 1;
+ if ((fptr = fopen(s, "rb")) == NULL) {
+ fprintf(stderr, "Failed to open file: %s.\n", s);
+ exit(EXIT_FAILURE);
+ }
+ }
+ argv++;
+ }
+
+ if (o_do_x)
+ ud_set_input_hook(&ud_obj, input_hook_x);
+ else ud_set_input_hook(&ud_obj, input_hook_file);
+
+ if (o_skip) {
+ o_count += o_skip;
+ ud_input_skip(&ud_obj, o_skip);
+ }
+
+ /* disassembly loop */
+ while (ud_disassemble(&ud_obj)) {
+ if (o_do_off)
+ printf("%016" FMT "x ", ud_insn_off(&ud_obj));
+ if (o_do_hex) {
+ char* hex1, *hex2;
+ char c;
+ hex1 = ud_insn_hex(&ud_obj);
+ hex2 = hex1 + 16;
+ c = hex1[16];
+ hex1[16] = 0;
+ printf("%-16s %-24s", hex1, ud_insn_asm(&ud_obj));
+ hex1[16] = c;
+ if (strlen(hex1) > 16) {
+ printf("\n");
+ if (o_do_off)
+ printf("%15s -", "");
+ printf("%-16s", hex2);
+ }
+ }
+ else printf(" %-24s", ud_insn_asm(&ud_obj));
+
+ printf("\n");
+ }
+
+ exit(EXIT_SUCCESS);
+ return 0;
+}
+
+int input_hook_x(ud_t* u)
+{
+ unsigned int c, i;
+
+ if (o_do_count) {
+ if (! o_count)
+ return UD_EOI;
+ else --o_count;
+ }
+
+ i = fscanf(fptr, "%x", &c);
+
+ if (i == EOF)
+ return UD_EOI;
+ if (i == 0) {
+ fprintf(stderr, "Error: Invalid input, should be in hexadecimal form (8-bit).\n");
+ return UD_EOI;
+ }
+ if (c > 0xFF)
+ fprintf(stderr, "Warning: Casting non-8-bit input (%x), to %x.\n", c, c & 0xFF);
+ return (int) (c & 0xFF);
+}
+
+int input_hook_file(ud_t* u)
+{
+ int c;
+
+ if (o_do_count) {
+ if (! o_count) {
+ return -1;
+ } else o_count -- ;
+ }
+
+ if ((c = fgetc(fptr)) == EOF)
+ return UD_EOI;
+ return c;
+}
--- /dev/null
+/* udis86 - udis86.h
+ *
+ * Copyright (c) 2002-2009 Vivek Thampi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef UDIS86_H
+#define UDIS86_H
+
+#include "libudis86/types.h"
+#include "libudis86/extern.h"
+#include "libudis86/itab.h"
+
+#endif
andersk / udis86.git / commitdiff
